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[ak4634] rev. 0.5 2007/10 - 1 - general description the ak4634 is a 16-bit mono codec with microphone-am plifier and speaker-amplif ier. input circuits include a microphone-amplifier and an alc (automatic level control) circ uit. output circuits include a speaker-amplifier and mono line out put. the ak4634 is suitable for a moving picture of digital still camera and etc. this speake r-amplifier supports a piezo s peaker. the ak4634 is housed in a space-saving 32-pin qfn 5mm x 5mm package. feature 1. 16-bit delta-sigma mono codec 2. recording function ? 1ch mono input ? mic amplifier: (0db/+3db/+6db/+10db/ +17db/+20db/+23db/+ 26db/+29db/+32db) ? digital alc (automatic level control) (+36db -54db, 0.375db step, mute) ? adc performance (mic-amp=+20db) - s/(n+d): 84db - dr, s/n: 86db ? wind-noise reduction emphasis ? 5 band notch filter 3. playback function ? digital alc (automatic level control) (+36db -54db, 0.375db step, mute) ? mono line output: s/(n+d) : 85db, s/n : 93db ? mono class-d speaker-amp - btl output - output power: 400mw @ 8 (svdd=3.3v) - s/(n+d): 55db (150mw@8 ) ? beep generator 4. power management 5. pll mode: ? frequencies: 12mhz, 13.5mhz, 24mhz, 27mhz (mcki pin) 1fs (fck pin) 16fs, 32fs or 64fs (bick pin) 6. ext mode: ? frequencies: 256fs, 512fs or 1024fs (mcki pin) 7. sampling rate: ? pll slave mode (fck pin): 7.35khz ~ 48khz ? pll slave mode (bick pin): 7.35khz ~ 48khz ? pll slave mode (mcki pin): 8khz, 11.025khz, 12khz, 16khz, 22.05kh z, 24khz, 32khz, 44.1khz, 48khz ? pll master mode: 8khz, 11.025khz, 12khz, 16khz, 22.05kh z, 24khz, 32khz, 44.1khz, 48khz ? ext slave mode / ext master mode: 7.35khz ~ 48khz (256fs), 7.35khz ~ 26khz (512fs), 7.35khz ~ 13khz (1024fs) 8. output master clock frequency: 256fs 9. serial p interface: 3-wire, i2c bus (ver 1.0, 400khz high speed mode) ak4634 16-bit mono codec with alc & mic/spk- a mp = preliminary =
[ak4634] rev. 0.5 2007/10 - 2 - 10. master / slave mode 11. audio interface format: msb first, 2?s compliment ? adc: dsp mode, 16bit msb justified, i 2 s ? dac: dsp mode, 16bit msb justif ied, 16bit lsb justified, i 2 s 12. ta = - 30 85 c 13. power supply ? analog supply (avdd): 2.2 3.6v ? digital supply (dvdd): 1.6 3.6v ? speaker supply (svdd): 2.2 4.0v 14. package: 29pin csp, 2.5mm x 3.0mm, 0.5mm pitch block diagram d/a mic power supply a/d hpf pmmp pmadc audio i/f pmdac & pmao line out pmspk speaker pll pmpll control register mpi mic/micp spp spn svdd vss3 avdd vss1 vcom dvdd cclk/scl cdtio bick fck sdto sdti mcko mcki vcoc pmao aout vss2 mic-amp 0db /+3db/+6db/+10db/+17db/+20db +23db+26db / +29db / +32db mic 5 band eq vol (alc) pmpfil class-d spk-amp csn/sda lpf hpf beep generator i2c lin/micn pdn pmspk smute pmdac datt tet1 tet2 tet3 figure 1. ak4634 block diagram
[ak4634] rev. 0.5 2007/10 - 3 - ordering guide ak4634 ? 30 +85 c 29 pin csp (0.5mm pitch) AKD4634 evaluation board for ak4634 pin layout a bc e d 6 5 3 4 1 2 top view 6 i2c dvdd vss2 vss3 nc 5 sdto mcko spn svdd spp 4 bick sdti mcki aout lin/ micn 3 fck cclk/scl cdtio mpi mic/ micp 2 pdn csn/sda tst2 vcom vcoc 1 tst1 vss1 avdd tst3 a b c d e top view
[ak4634] rev. 0.5 2007/10 - 4 - compatibility with ak4633 1. function function ak4633 ak4634 mic-amp 0db/+6db/+10db/+14db +17db/+20db/+26db/+32db 0db/+3db/+6db/+10db/+17db/ +20db/+23db/+26db/+29db/ +32db single end of analog input 1ch (mic pin) 2ch (mic pin / lin pin) lpf not available available notch filter ( equalizer) 2 band 5 band spk-amp class-ab class-d alc recovery waiting period 4 steps (128fs ~ 1024fs) 8 steps (128fs ~ 16384fs) master clock mode pll mode frequency 11.2896mhz, 12mhz, 12.288mhz, 13.5mhz 24mhz, 27mhz 12mhz, 13.5mhz, 24mhz, 27mhz beep output analog input generator circuit included control interface 3-wire 3-wire, i 2 c package 24pin qfn: 4.0mm x 4.0mm 29 pin csp:2.5mm x 3.0mm
[ak4634] rev. 0.5 2007/10 - 5 - pin/function no. pin name i/o function 1 nc - no connection. no internal bonding. this pin should be connected to the ground. 2 tst3 - test3 pin this p in should be o p en. 3 avdd - analog power supply pin 2.2 ~ 3.6v 4 vss1 - ground pin. 5 tst2 - test2 pin this p in should be o p en. 6 tst1 - test1 pin this p in should be o p en. 7 nc - no connection. no internal bonding. this pin should be connected to the ground. csn i chip select pin (i2c pin = ?l?) 8 sda i/o control data input/output pin (i2c pin = ?h?) 9 pdn i power-down mode pin ?h?: power up, ?l?: power down reset and initialize the control register. ak4634 should always be reset upon power-up. 10 cdtio i/o control data input/output pin (i2c pin = ?l?) this pin should be connected to the ground. (i2c pin = ?h?) cclk i control data clock pin (i2c pin = ?l?) 11 scl i control data clock pin (i2c pin = ?h?) 12 fck i/o frame clock pin 13 mcki i external master clock input pin 14 bick i/o audio serial data clock pin 15 sdti i audio serial data input pin 16 sdto o audio serial data output pin 17 i2c i control mode select pin ?h?: i 2 c bus, ?l?: 3-wire serial 18 mcko o master clock output pin 19 dvdd - digital power supply pin 1.6 ~ 3.6v 20 vss2 - ground pin. 21 nc - no connection. no internal bonding. this pin should be connected to the ground. 22 spn o speaker amp negative output pin 23 vss3 - ground pin. 24 nc - no connection. no internal bonding. this pin should be connected to the ground. 25 spp o speaker amp negative output pin 26 svdd - speaker amp power supply pin 2.2 ~4.0v 27 aout o mono line output pin lin i line input pin for single ended input (mdif bit = ?0?) 28 micn i microphone negative input pin for differential input (mdif bit = ?1?) mic i microphone input pin for single ended input (mdif bit = ?0?) 29 micp i microphone positive input pin for differential input (mdif bit = ?1?) 30 mpi i mic power supply pin for microphone 31 vcom o common voltage output pin, 0.45 x avdd bias voltage of adc inputs and dac outputs. 32 vcoc o output pin for loop filter of pll circuit this pin should be connected to vss1 with one resistor and capacitor in series. note : all input pins except analog input pins (mic/micp, lin/micn pins) must not be left floating
[ak4634] rev. 0.5 2007/10 - 6 - handling of unused pin the unused i/o pins should be processed appropriately as below. classification pin name setting analog mic/micp, lin/micn, mpi, aout, spp, spn, vcoc these pins should be open mcki, sdti these pins should be connected to vss2 cdtio when i2c pin = ?h?, these pins should be connected to vss2. digital mcko, sdto these pins should be open. absolute maximum ratings (vss1-3 =0v; note 1 ) parameter symbol min max units power supplies: analog digital speaker-amp avdd dvdd svdd ? 0.3 ? 0.3 ? 0.3 4.6 4.6 4.6 v v v input current, any pin except supplies iin - 10 ma analog input voltage ( note 2 ) vina ? 0.3 avdd+0.3 v digital input voltage ( note 3 ) vind ? 0.3 dvdd+0.3 v ambient temperature (powered applied) ta ? 40 85 c storage temperature tstg ? 65 150 c maximum power dissipation ( note 4 ) pd - 400 mw note 1. all voltages with respect to ground. vss21, vss2 and vss3 must be connected to the same analog ground plane. note 2. lin/micn, mic/micp pins note 3. pdn, i2c, csn/sda, cclk/scl, cdtio, sdti, fck, bick, mcki pins pull-up resistors at sda and scl pins should be connected to (dvdd+0.3)v or less voltage. note 4.when pcb wiring density is 100%. this power is the ak4634 internal dissipation that does not include power of externally connected speaker. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss1-3=0v; note 1 ) parameter symbol min typ max units power supplies ( note 5 ) analog digital speaker-amp avdd dvdd svdd 2.2 1.6 2.2 3.3 3.3 3.3 3.6 3.6 4.0 v v v note 1. all voltages with respect to ground. note 5. the power up sequence betw een avdd, dvdd and svdd is not critical. do not power dvdd off when avdd or svdd is powered up. when only avdd or svdd is powered off, the ak4634 must be reset by bringing the pdn pin ?l? after theses power supplies are powered on again. the power supply current of dvdd at power-down mode may be increased. dvdd should not be powered off while avdd or svdd is powered on. * akemd assumes no responsibility for the usag e beyond the conditions in this datasheet.
[ak4634] rev. 0.5 2007/10 - 7 - analog chracteristics (ta=25 c; avdd = dvdd = svdd=3.3v; vss1-3 =0v; fs=8khz, bick=64fs; signal frequency=1khz; 16bit data; measurement frequency=20hz 3.4khz; ext slave mode; unless otherwise specified) parameter min typ max units mic amplifier: mic, lin pins ; mdif bit = ? 0 ? ; (single-ended input) input resistance 20 30 40 k gain (mgain3-0 bits = ? 0000 ? ) - 0 - db (mgain3-0 bits = ? 0001 ? ) - 20 - db (mgain3-0 bits = ? 0010 ? ) - 26 - db (mgain3-0 bits = ? 0011 ? ) - 32 - db (mgain3-0 bits = ? 0100 ? ) - 10 - db (mgain3-0 bits = ? 0101 ? ) - 17 - db (mgain3-0 bits = ? 0110 ? ) - 23 - db (mgain3-0 bits = ? 0111 ? ) - 29 - db (mgain3-0 bits = ? 1000 ? ) - 3 - db (mgain3-0 bits = ? 1001 ? ) - 6 - db mic amplifier: micp, micn pins ; mdif bit = ? 1 ? ; (full-differential input) input voltage (mgain3-0 bits = ? 0001 ? ) - - 0.228 vpp ( note 6 ) (mgain3-0 bits = ? 0010 ? ) - - 0.114 vpp (mgain3-0 bits = ? 0011 ? ) - - 0.057 vpp (mgain3-0 bits = ? 0100 ? ) - - 0.720 vpp (mgain3-0 bits = ? 0101 ? ) - - 0.322 vpp (mgain3-0 bits = ? 0110 ? ) - - 0.161 vpp (mgain3-0 bits = ? 0111 ? ) - - 0.080 vpp (mgain3-0 bits = ? 1001 ? ) - - 1.14 vpp mic power supply: mpi pin output voltage ( note 7 ) tbd 2.64 tbd v load resistance 2 - - k load capacitance - - 30 pf adc analog input characteristics: mic/lin ? adc, mic gain=20db, ivol=0db, alc1bit = ? 0 ? resolution - - 16 bits input voltage (mic gain=20db, note 8 ) tbd 0.198 tbd vpp s/(n+d) ( ? 1dbfs) ( note 9 ) tbd 84 - db d-range ( ? 60dbfs) tbd 86 - db s/n tbd 86 - db dac characteristics: resolution 16 bits mono line output characteristics: aout pin, dac aout, r l =10k output voltage ( note 10 ) lovl bit = ?0? tbd 1.98 tbd vpp lovl bit = ?1? tbd 2.50 tbd vpp s/(n+d) (0dbfs) ( note 9 ) tbd 85 - db d-range (-60dbfs) tbd 93 - db s/n tbd 93 - db load resistance 10 - - k load capacitance - - 30 pf speaker-amp characteristics: sdti ? spp/spn pins, alc2 bit = ? 0 ? , spkg bit = ?0?, r l =8 + 10 h, btl = svdd=3.3v output power (0dbfs) ( note 11 ) - 400 - mw s/(n+d) 400mw output - 20 - db 150mw output - 55 - db output noise level tbd -80 - dbv load resistance 8 - - load capacitance - - 30 pf
[ak4634] rev. 0.5 2007/10 - 8 - parameter min typ max units speaker-amp characteristics: sdti spp/spn pins, alc2 bit = ?0?, spkg bit = ?0?, c l =3 f, r series =10 x 2, btl, svdd=3.8v output voltage (0dbfs) ( note 11 ) - 2.5 - vrms s/(n+d) ( note 12 ) - 20 - db output noise level ( note 12 ) - -68 - dbv load impedance ( note 13 ) 50 - - load capacitance - - 3 f power supplies power up (pdn pin = ?h?) all circuit power-up: ( note 17 ) avdd+dvdd fs=8khz - 9 - ma fs=48khz - 12 tbd ma svdd: speaker-amp normal operation (no output) svdd=3.3v - 1.5 tbd ma power down (pdn pin = ?l?) ( note 18 ) avdd+dvdd+svdd - 1 tbd a note 6. the voltage difference between micp and micn pins . ac coupling capacitor should be connected in series at each input pin. full-differential mic i nput is not available at mgain3-0 b its = ?1000? or ?0000?. maximum input voltage of micp and micn pins are proportional to avdd voltage, respectively. vin = |(micp) ? (micn)| = 0.069 x avdd(max)@mgain3-0 bits = ?0001?, 0.035 x avdd(max)@mgain3-0 bits = ?0010?, 0.017 x avdd(max)@mgain3-0 bits = ?0011?, 0.218x avdd(max)@mgain3-0 bits = ?0100?, 0.097x avdd(max)@mgain3-0 bits = ?0101?, 0.048x avdd(max)@mgain3-0 bits = ?0110?, 0.024x avdd(max)@mgain3-0 bits = ?0111?, 0.345x avdd(max)@mgain3-0 bits = ?1001? when the signal larger than above value is input to micp or micn pin, adc does not operate normally. note 7. output voltage is proportional to avdd voltage. vout = 0.8 x avdd (typ) note 8. input voltage is proportional to avdd voltage. vin = 0.06 x avdd (typ) note 9. when a pll reference clock is the fck pin in pll slave mode, s/ (n+d) of mic ? adc is 75db (typ), s/ (n+d) of dac ? aout is 75db (typ). note 10. output voltage is proportional to avdd voltage. vout = 0.6 x avdd (typ)@lovl bit = ?0?. note 11. the value after passing lpf (lpf : passband is 20khz or less, stopband attenuation@250khz is ?50db or less) note 12. in case of measuring at be tween the spp pin and spn pin directly. note 13. load impedance is total impedance of series resistance (r series ) and piezo speaker impedance at 1khz in figure 44 . load capacitance is capacita nce of piezo speaker. when piezo speaker is used, 10 or more series resistors should be conn ected at both spp and spn pins, respectively. note 14. maximum input voltage is in proportion to both avdd and external input resistance (rin). vin = 0.6 x avdd x rin/20k (typ). note 15. output voltage is proportional to avdd voltage. vout = 0.6 x avdd (typ). note 16. input voltage does not depend on avdd voltage. note 17. pll master mode (mcki = 12mhz) and p mmp = pmadc = pmdac = pmpfil = pmspk = pmvcm = pmpll = mcko = pmao = m/s = ?1?. and output current from the mpi pin is 0ma. ext slave mode (pmpll = m/s = mcko bits = ?0?): avdd+dvdd = (typ) tbdma@fs=8khz, (typ)tbdma @fs=48khz note 18. all digital inputs pins are fixed to dvdd or vss2.
[ak4634] rev. 0.5 2007/10 - 9 - filter chracteristics (ta = ? 30 85 c; avdd = 2.2 3.6v; dvdd = 1.6 3.6v, svdd = 2.2 4.0v; fs=8khz) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 19 ) 0.16db ? 0.66db ? 1.1db ? 6.9db pb 0 - - - - 3.5 3.6 4.0 3.0 - - - khz khz khz khz stopband ( note 19 ) sb 4.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 73 - - db group delay ( note 20 ) gd - 16 - 1/fs group delay distortion gd - 0 - s dac digital filter (decimation lpf): passband ( note 19 ) 0.16db ? 0.54db ? 1.0db ? 6.7db pb 0 - - - - 3.5 3.6 4.0 3.0 - - - db stopband ( note 19 ) sb 4.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 73 - - db group delay ( note 20 ) gd - 16 - 1/fs group delay distortion gd - 0 - s dac digital filter + analog filter: frequency response: 0 3.4khz fr - 1.0 - db note 19. the passband and stopband frequencies ar e proportional to fs (system sampling rate). for example, adc of pb = 3.6khz is 0.45*fs (@ ? 1.0db). a reference of frequency response is 1khz. note 20. the calculated delay time caused by digital filtering. this time is from the input of analog signal to setting of the 16-bit data of a channel from the input register to the output register of the adc. for the dac, this time is from setting the 16-bit data of a channel from the input register to the output of analog signal. when there is not a phase change with the iir filter, the group delay of the programmable filter (primary hpf + primary lpf + 5-band equalizer + alc) increases for 2/fs than a value of an above mention. dc chracteristics (ta = ? 30 ~ 85 c; avdd = 2.2 3.6v, dvdd = 1.6 3.6v, svdd = 2.2 4.0v) parameter symbol min typ max units high-level input voltage (dvdd 2.2v) (dvdd < 2.2v) low-level input voltage (dvdd 2.2v) (dvdd < 2.2v) vih vil 70%dvdd 80%dvdd - - - - - - - - 30%dvdd 20%dvdd v v v v high-level output voltage (iout = ? 80 a) low-level output voltage (except sda pin: iout = 80 a) (sda pin, 2.0v dvdd 3.6v: iout = 3ma) (sda pin, 1.6v dvdd < 2.0v: iout = 3ma) voh vol1 vol2 vol2 dvdd ? 0.2 - - - - - - - - 0.2 0.4 20%dvdd v v v input leakage current iin - - 10 a
[ak4634] rev. 0.5 2007/10 - 10 - switing characteristics (ta = ? 30 ~ 85 c; avdd = 2.2 3.6v, dvdd = 1.6 3.6v, svdd = 2.2 4.0v; c l = 20pf) parameter symbol min typ max units pll master mode (pll reference clock = mcki pin) ( figure 2 ) mcki input: frequency pulse width low pulse width high fclk tclkl tclkh 11.2896 0.4/fclk 0.4/fclk - - - 27.0 - - mhz ns ns mcko output: frequency duty cycle except fs=29.4khz, 32khz fs =29.4khz, 32khz ( note 21 ) fmck dmck dmck - 40 - 256 x ffck 50 33 - 60 - khz % % fck output: frequency pulse width high (dif1-0 bits = ?00? and fcko bit = ?1?) duty cycle (dif1-0 bits = ?00? or fcko bit = ?0?) ffck tfckh dfck 8 - - - tbck 50 48 - - khz ns % bick: period (bcko1-0 = ?00?) (bcko1-0 = ?01?) (bcko1-0 = ?10?) duty cycle tbck tbck tbck dbck - - - - 1/16ffck 1/32ffck 1/64ffck 50 - - - - ns ns ns % audio interface timing dsp mode: ( figure 3 , figure 4 ) fck ? ? to bick ? ? ( note 22 ) fck ? ? to bick ? ? ( note 23 ) bick ? ? to sdto (bckp = ?0?) bick ? ? to sdto (bckp = ?1?) sdti hold time sdti setup time tdbf tdbf tbsd tbsd tsdh tsds 0.5 x tbck ? 40 0.5 x tbck ? 40 -70 -70 50 50 0.5 x tbck 0.5 x tbck - - - - 0.5 x tbck + 40 0.5 x tbck +40 70 70 - - ns ns ns ns ns ns except dsp mode: ( figure 5 ) bick ? ? to fck edge fck to sdto (msb) (except i 2 s mode) bick ? ? to sdto sdti hold time sdti setup time tbfck tfsd tbsd tsdh tsds ? 40 ? 70 ? 70 50 50 - - - - - 40 70 70 - - ns ns ns ns ns
[ak4634] rev. 0.5 2007/10 - 11 - parameter symbol min typ max units pll slave mode (pll reference clock: fck pin) ( figure 6 , figure 7 ) fck: frequency dsp mode: pulse width high except dsp mode: duty cycle ffck tfckh duty 7.35 tbck ? 60 45 8 - - 48 1/ffck ? tbck 55 khz ns % bick: period pulse width low pulse width high tbck tbckl tbckh 1/64ffck 0.4 x tbck 0.4 x tbck - - - 1/16ffck - - ns ns ns pll slave mode (pll reference clock: bick pin) ( figure 6 , figure 7 ) fck: frequency dsp mode: pulse width high except dsp mode: duty cycle ffck tfckh duty 7.35 tbck ? 60 45 8 - - 48 1/ffck ? tbck 55 khz ns % bick: period (pll3-0 bit = ?0001?) (pll3-0 bit = ?0010?) (pll3-0 bit = ?0011?) pulse width low pulse width high tbck tbck tbck tbckl tbckh - - - 0.4 x tbck 0.4 x tbck 1/16ffck 1/32ffck 1/64ffck - - - - - - - ns ns ns ns ns pll slave mode (pll reference clock: mcki pin) ( figure 8 ) mcki input: frequency pulse width low pulse width high fclk fclkl fclkh 11.2896 0.4/fclk 0.4/fclk - - - 27.0 - - mhz ns ns mcko output: frequency duty cycle except fs=29.4khz, 32khz fs=29.4khz, 32khz ( note 21 ) fmck dmck dmck - 40 - 256 x ffck 50 33 - 60 - khz % % fck: frequency dsp mode: pulse width high except dsp mode: duty cycle ffck tfckh duty 8 tbck ? 60 45 - - - 48 1/ffck ? tbck 55 khz ns % bick: period pulse width low pulse width high tbck tbckl tbckh 1/64ffck 0.4 x tbck 0.4 x tbck - - - 1/16ffck - - ns ns ns audio interface timing dsp mode: ( figure 9 , figure 10 ) fck ? ? to bick ? ? ( note 22 ) fck ? ? to bick ? ? ( note 23 ) bick ? ? to fck ? ? ( note 22 ) bick ? ? to fck ? ? ( note 23 ) bick ? ? to sdto (bckp bit= ?0?) bick ? ? to sdto (bckp bit= ?1?) sdti hold time sdti setup time tfckb tfckb tbfck tbfck tbsd tbsd tsdh tsds 0.4 x tbck 0.4 x tbck 0.4 x tbck 0.4 x tbck - - 50 50 - - - - - - - - - - - - 80 80 - - ns ns ns ns ns ns ns ns except dsp mode: ( figure 12 ) fck edge to bick ? ? ( note 24 ) bick ? ? to fck edge ( note 24 ) fck to sdto (msb) (except i 2 s mode) bick ? ? to sdto sdti hold time sdti setup time tfckb tbfck tfsd tbsd tsdh tsds 50 50 - - 50 50 - - - - - - - - 80 80 - - ns ns ns ns ns ns
[ak4634] rev. 0.5 2007/10 - 12 - parameter symbol min typ max units ext slave mode ( figure 11 ) mcki frequency: 256fs 512fs 1024fs pulse width low pulse width high fclk fclk fclk tclkl tclkh 1.8816 3.7632 7.5264 0.4/fclk 0.4/fclk 2.048 4.096 8.192 - - 12.288 13.312 13.312 - - mhz mhz mhz ns ns fck frequency (mcki = 256fs) (mcki = 512fs) (mcki = 1024fs) duty cycle ffck ffck ffck duty 7.35 7.35 7.35 45 8 8 8 - 48 26 13 55 khz khz % bick period bick pulse width low pulse width high tbck tbckl tbckh 312.5 130 130 - - - - - - ns ns ns audio interface timing ( figure 12 ) fck edge to bick ? ? ( note 24 ) bick ? ? to fck edge ( note 24 ) fck to sdto (msb) (except i 2 s mode) bick ? ? to sdto sdti hold time sdti setup time tfckb tbfck tfsd tbsd tsdh tsds 50 50 - - 50 50 - - - - - - - - 80 80 - - ns ns ns ns ns ns
[ak4634] rev. 0.5 2007/10 - 13 - parameter symbol min typ max units ext master mode ( figure 2 ) mcki frequency: 256fs 512fs 1024fs pulse width low pulse width high fclk fclk fclk tclkl tclkh 1.8816 3.7632 7.5264 0.4/fclk 0.4/fclk 2.048 4.096 8.192 - - 12.288 13.312 13.312 - - mhz mhz mhz ns ns fck frequency (mcki = 256fs) (mcki = 512fs) (mcki = 1024fs) duty cycle ffck ffck ffck dfck 7.35 7.35 7.35 - 8 8 8 50 48 26 13 - khz khz khz % bick: period (bcko1-0 bit = ?00?) (bcko1-0 bit = ?01?) (bcko1-0 bit = ?10?) duty cycle tbck tbck tbck dbck - - - - 1/16ffck 1/32ffck 1/64ffck 50 - - - - ns ns ns % audio interface timing dsp mode: ( figure 3 , figure 4 ) fck ? ? to bick ? ? ( note 22 ) fck ? ? to bick ? ? ( note 23 ) bick ? ? to sdto (bckp bit = ?0?) bick ? ? to sdto (bckp bit = ?1?) sdti hold time sdti setup time tdbf tdbf tbsd tbsd tsdh tsds 0.5 x tbck ? 40 0.5 x tbck ? 40 ? 70 ? 70 50 50 0.5 x tbck 0.5 x tbck - - - - 0.5 x tbck + 40 0.5 x tbck +40 70 70 - - ns ns ns ns ns ns except dsp mode: ( figure 5 ) bick ? ? to fck edge fck to sdto (msb) (except i 2 s mode) bick ? ? to sdto sdti hold time sdti setup time tbfck tfsd tbsd tsdh tsds ? 40 ? 70 ? 70 50 50 - - - - - 40 70 70 - - ns ns ns ns ns note 21. duty cycle = (the width of ?l?)/(the period of clock)*100 note 22. msbs, bckp bits = ?00? or ?11? note 23. msbs, bckp bits = ?01? or ?10? note 24. bick rising edge must not occur at the same time as fck edge.
[ak4634] rev. 0.5 2007/10 - 14 - parameter symbol min typ max units control interface timing (3-wire serial mode) cclk period tcck 200 - - ns cclk pulse width low tcckl 80 - - ns pulse width high tcckh 80 - - ns cdti setup time tcds 40 - - ns cdti hold time tcdh 40 - - ns csn ?h? time tcsw 150 - - ns csn ? ? to cclk ? ? tcss 50 - - ns cclk ? ? to csn ? ? tcsh 50 - - ns cclk ? ? to cdti (at read command) tdcd - - 70 ns csn ? ? to cdti (hi-z) (at read command) tccz - - 70 ns control interface timing (i 2 c bus mode): scl clock frequency fscl - - 400 khz bus free time between transmissions tbuf 1.3 - - s start condition hold time (prior to first clock pulse) thd:sta 0.6 - - s clock low time tlow 1.3 - - s clock high time thigh 0.6 - - s setup time for repeated start condition tsu:sta 0.6 - - s sda hold time from scl falling ( note 26 ) thd:dat 0 - - s sda setup time from scl rising tsu:dat 0.1 - - s rise time of both sda and scl lines tr - - 0.3 s fall time of both sda and scl lines tf - - 0.3 s setup time for stop condition tsu:sto 0.6 - - s capacitive load on bus cb - - 400 pf pulse width of spike noise suppressed by input filter tsp 0 - 50 ns reset timing pdn pulse width ( note 25 , note 26 , note 27 ) tpd 150 - - ns pmadc ? ? to sdto valid ( note 28 ) adrst bit = ?0? tpdv - 1059 - 1/fs adrst bit = ?1? tpdv - 291 - 1/fs note 25. i 2 c is a registered trademark of philips semiconductors. note 26. r l = 1k ? /10% change ( pull-up to dvdd) note 27. the ak4634 can be reset by the pdn pin = ?l? note 28. this is the count of fck ? ? from the pmadc = ?1?.
[ak4634] rev. 0.5 2007/10 - 15 - timing diagram fck 1/fclk mcki tclkh tclkl vih vil 1/fmck mcko tmckoh tmckol 50%dvdd 1/ffck dfck dfck 50%dvdd dmck = tmckol x fmck x 100% figure 2. clock timing (pll/ext master mode) (mcko is not available at ext master mode) fck bick 50%dvdd sdto 50%dvdd tbsd tsds sdti vil tsdh vih dbck tdbf 50%dvdd tbck msb msb bick 50%dvdd (bckp = "0") (bckp = "1") figure 3. audio interface timing (pll/ext ma ster mode & dsp mode: msbs = ?0?)
[ak4634] rev. 0.5 2007/10 - 16 - fck bick 50%dvdd sdto 50%dvdd tbsd tsds sdti vil tsdh vih dbck tdbf 50%dvdd tbck msb bick 50%dvdd (bckp = "1") (bckp = "0") msb figure 4. audio interface timing (pll/ext ma ster mode & dsp mode: msbs = ?1?) fck 50%dvdd bick 50%dvdd sdto 50%dvdd tbsd tsds sdti vil tsdh vih tbfck dbck tfsd figure 5. audio interface timing (pll/ex t master mode & except dsp mode)
[ak4634] rev. 0.5 2007/10 - 17 - 1/ffck fck vih tfckh vil tbck bick tbckh tbckl vih vil tbfck bick vih vil (bckp = "0") (bckp = "1") figure 6. clock timing (pll slave mode; pll reference clock = fck or bick pin & dsp mode; msbs = ?0?) 1/ffck fck vih tfckh vil tbck bick tbckh tbckl vih vil tbfck bick vih vil (bckp = "1") (bckp = "0") figure 7. clock timing (pll slave mode; pll reference clock = fck or bick pin & dsp mode; msbs = ?1?)
[ak4634] rev. 0.5 2007/10 - 18 - 1/fclk mcki tclkh tclkl vih vil 1/ffck fck vih vil tbck bick tbckh tbckl vih vil tfckh tfckl 1/fmck mcko 50%dvdd tmckoh tmckol dmck = tmckol x fmck x 100% figure 8. clock timing (pll slave mode; pll reference clock = mcki pin & except dsp mode)
[ak4634] rev. 0.5 2007/10 - 19 - fck bick sdto 50%dvdd tbsd tsds sdti vil tsdh vih tfckb tfckh msb msb vil vih vil vih bick vil vih (bckp = "0") (bckp = "1") figure 9. audio interface timing (pll slave mode & dsp mode; msbs = ?0?) fck bick sdto 50%dvdd tbsd tsds sdti vil tsdh vih tfckb tfckh msb msb vil vih vil vih bick vil vih (bckp = "1") (bckp = "0") figure 10. audio interface timing (pll slave mode, dsp mode; msbs = ?1?)
[ak4634] rev. 0.5 2007/10 - 20 - 1/fclk mcki tclkh tclkl vih vil 1/ffck fck vih vil tbck bick tbckh tbckl vih vil tfckh tfckl figure 11. clock timing (ext slave mode) fck vih vil tbfck bick vih vil tfsd sdto 50%dvdd tfckb tbsd tsds sdti vil tsdh vih msb figure 12. audio interface timing (pll, ext slave mode & except dsp mode)
[ak4634] rev. 0.5 2007/10 - 21 - csn vih vil tcss cclk tcds vih vil cdti vih tcckh tcckl tcdh vil c1 c0 r/w tcck figure 13. write command input timing csn vih vil tcsh cclk vih vil cdti vih tcsw vil d1 d0 d2 figure 14. write data input timing
[ak4634] rev. 0.5 2007/10 - 22 - csn cclk 50% dvdd cdti vih d3 d2 d1 d0 tccz tdcd vil vih vil figure 15. read data output timing stop start start stop thigh thd:dat sda scl tbuf tlow tr tf tsu:dat vih vil thd:sta tsu:sta vih vil tsu:sto tsp figure 16. i 2 c bus mode timing pmadc tpdv sdto 50%dvdd bit figure 17. power down & reset timing 1 tpd pdn vil figure 18. power down & reset timing 2
[ak4634] rev. 0.5 2007/10 - 23 - operation overview system clock there are the following five clock modes to interface with external devices. ( table 1 and table 2 ) mode pmpll bit m/s bit pll3-0 bit figure pll master mode 1 1 table 4 figure 19 pll slave mode 1 (pll reference clock: mcki pin) 1 0 table 4 figure 20 pll slave mode 2 (pll reference clock: fck or bick pin) 1 0 table 4 figure 21 figure 22 ext slave mode 0 0 x figure 23 ext master mode 0 1 x figure 24 table 1. clock mode setting (x: don?t care) mode mcko bit mcko pin mcki pin bick pin fck pin 0 ?l? output pll master mode 1 256fs output master clock input for pll ( note 29 ) 16fs/32fs/64fs output 1fs output 0 ?l? output pll slave mode 1 (pll reference clock: mcki pin) 1 256fs output master clock input for pll ( note 29 ) 16fs input 1fs input pll slave mode 2 (pll reference clock: fck or bick pin) 0 ?l? output gnd 16fs/32fs/64fs input 1fs input ext slave mode 0 ?l? output 256fs/ 512fs/ 1024fs input 32fs input 1fs input ext master mode 0 ?l? output 256fs/ 512fs/ 1024fs input 32fs/64fs output 1fs output note 29. 12mhz/13.5mhz/24mhz/27mhz table 2. clock pins state in clock mode
[ak4634] rev. 0.5 2007/10 - 24 - master mode/slave mode the m/s bit selects either master or slav e modes. m/s bit = ?1? selects master m ode and ?0? selects slave mode. when the ak4634 is in power-down mode (pdn pin = ?l?) and exits re set state, the ak4634 is slave mode. after exiting reset state, the ak4634 changes to master mode by bringing m/s bit = ?1?. when the ak4634 is in master mode, fck and bick pins ar e a floating state until m/s bit becomes ?1?. the fck and bick pins of the ak4634 should be pulled-down or pulled-up by about 100k resistor externally to avoid the floating state. m/s bit mode 0 slave mode (default) 1 master mode table 3. select master/salve mod pll mode when pmpll bit is ?1?, a fully integrated analog phase lock ed loop (pll) generates a clock that is selected by the pll3-0 and fs3-0 bits. the pll lock time is shown in table 4 . ether when the ak4634 is supplied to a stable clocks after pll is powered-up (pmpll bit = ?0? ?1?) or when the sampling frequency changes, the pll lock time is the same. 1) setting of pll mode r and c of vcoc pin ( note 30 ) mode pll3 bit pll2 bit pll1 bit pll0 bit pll reference clock input pin input frequency r[ ] c[f] pll lock time (max) 0 0 0 0 0 fck pin 1fs 6.8k 220n 160ms (default) 1 0 0 0 1 bick pin 16fs 10k 4.7n 2ms 2 0 0 1 0 bick pin 32fs 10k 4.7n 2ms 3 0 0 1 1 bick pin 64fs 10k 4.7n 2ms 6 0 1 1 0 mcki pin 12mhz 10k 4.7n 20ms 7 0 1 1 1 mcki pin 24mhz 10k 4.7n 20ms 12 1 1 0 0 mcki pin 13.5mhz 10k 10n 20ms 13 1 1 0 1 mcki pin 27mhz 10k 10n 20ms others others n/a note 30. the tolerance of r is 5%, the tolerance of c is 30% table 4. setting of pll mode (*fs: sampling frequency, n/a: not available) 2) setting of sampling frequency in pll mode. when pll2 bit is ?1? (pll reference clock input is the mcki pin), the sampling frequency is selected by fs2-0 bits as defined in table 5 . mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency 0 0 0 0 0 8khz (default) 1 0 0 0 1 12khz 2 0 0 1 0 16khz 3 0 0 1 1 24khz 4 0 1 0 0 7.35khz 5 0 1 0 1 11.025khz 6 0 1 1 0 14.7khz 7 0 1 1 1 22.05khz 10 1 0 1 0 32khz 11 1 0 1 1 48khz 14 1 1 1 0 29.4khz 15 1 1 1 1 44.1khz others others n/a table 5. setting of sampling frequency at pll2 bit = ?1? and pmpll bit = ?1? (n/a: not available)
[ak4634] rev. 0.5 2007/10 - 25 - when pll2 bit is ?0? (pll reference clock input is fck or bick pin), the sampling frequency is selected by fs3-2 bits. ( table 6 ) mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency range 0 0 0 x x 7.35khz fs 12khz (default) 1 0 1 x x 12khz < fs 24khz 2 1 0 x x 24khz < fs 48khz others others n/a (x: don?t care, n/a: not available) table 6. setting of sampling frequency at pll2 bit = ?0? and pmpll bit = ?1? pll unlock state 1) pll master mode (pmpll bit = ?1?, m/s bit = ?1?) in this mode, irregular frequency clocks are output from fck, bick and mcko pins after pmpll bit = ?0? ? ?1? or sampling frequency is changed. after that pll is unlocked, the bick and fck pins output ?l? for a moment, and invalid frequency clock is output from the mcko pin at mcko bit = ?1?. if the mcko bit is ?0?, mcko pin is output to ?l?. ( table 7 ) when sampling frequency is changed, bick and fck pins do not output irregular frequency clocks but go to ?l? by setting pmpll bit to ?0?. mcko pin pll state mcko bit = ?0? mcko bit = ?1? bick pin fck pin after that pmpll bit ?0? ? ?1? ?l? output invalid ?l? output ?l? output pll unlock ?l? output invalid invalid invalid pll lock ?l? output 256fs output see table 9 1fs output table 7. clock operation at pll master mode (pmpll bit = ?1?, m/s bit = ?1?) 2) pll slave mode (pmpll b it = ?1?, m/s bit = ?0?) in this mode, an invalid clock is output from the mcko pin after pmpll bit = ?0? ? ?1? or sampling frequency is changed. after that, 256fs is output from the mcko pin when pll is locked. adc and dac output invalid data when the pll is unlocked. for dac, the output signal should be muted by writing ?0? to daca and dacs bits in addr=02h. mcko pin pll state mcko bit = ?0? mcko bit = ?1? after that pmpll bit ?0? ? ?1? ?l? output invalid pll unlock ?l? output invalid pll lock ?l? output output table 8. clock operation at pll slave mode (pmpll bit = ?1?, m/s bit = ?0?)
[ak4634] rev. 0.5 2007/10 - 26 - pll master mode (pmpll bit = ?1?, m/s bit = ?1?) when an external clock (12mhz, 13.5mhz, 24mhz or 27mhz) is input to the mcki pin, the mcko, bick and fck clocks are generated by an internal pll circuit. the mcko output frequency is fixed to 256fs, the output is enabled by mcko bit. the bick is selected among 16fs, 32fs or 64fs, by bcko1-0 bits. ( table 9 ) in dsp mode, fck output can select duty 50% or high-output only during 1 bick cycle ( table 10 ). except dsp mode, fcko bit should be set ?0?. when bick output frequency is 16fs, the audio in terface format supports m ode 0 only (dsp mode). ak4634 dsp or p mcko bick fck sdto sdti bclk fck sdti sdto mcki 1fs 16fs, 32fs, 64fs 256fs 12mhz, 13.5mhz, 24mhz, 27mhz mclk figure 19. pll master mode mode bcko1 bcko0 bick output frequency 0 0 0 16fs (default) 1 0 1 32fs 2 1 0 64fs 3 1 1 n/a table 9. bick output frequency at master mode (n/a: not available) mode fcko fck output 0 0 duty = 50% (default) 1 1 high width = 1/fbck note 31. fbck is bick output frequency. table 10. fck output at pll master mode and dsp mode
[ak4634] rev. 0.5 2007/10 - 27 - pll slave mode (pmpll bit = ?1?, m/s bit = ?0?) a reference clock of pll is selected among the input clocks to the mcki, bick or fck pin. the required clock to the ak4634 is generated by an internal pll circuit. input frequenc y is selected by pll3-0 bits. when bick input frequency is 16fs, the audio interface format supports mode 0 only (dsp mode). a) pll reference clock: mcki pin bick and fck inputs should be synchronized with mcko output. the phase between mcko and fck is not important. the mcko pin outputs the frequency selected by fs3-0 bits ( table 5 ) ak4634 dsp or p mcko bick fck sdto sdti bclk fck sdti sdto mcki 1fs 16fs, 32fs, 64fs 256fs 12mhz, 13.5mhz, 24mhz, 27mhz mclk figure 20. pll slave mode 1 (pll reference clock: mcki pin)
[ak4634] rev. 0.5 2007/10 - 28 - b) pll reference clock: bick or lrck pin sampling frequency corresponds to 7.35khz to 48khz by changing fs3-0 bits. ( table 6 ) ak4634 dsp or p mcki bick fck sdto sdti bclk fck sdti sdto mcko 1fs 16fs, 32fs, 64fs figure 21 pll slave mode 2 (pll reference clock: bick pin) ak4634 dsp or p mcki bick fck sdto sdti bclk fck sdti sdto mcko 1fs 16fs figure 22. pll slave mode 2 (pll reference clock: fck pin) the external clocks (mcki, bick and fck) should always be present whenever the adc or dac or spk or programmable filter is in operation (pmadc bit = ?1?, pmdac bit = ?1?, pmspk bit = ?1?, pmpfil bit = ?1?). if these clocks are not provided, the ak4634 may dr aw excess current and it is not possibl e to operate properly because utilizes dynamic refreshed logic internally. if the external clocks are not present, the adc, dac, spk and programmable filter should be in the power-down mode.(pmadc = pmdac = pmspk = pmpfil bits = ?0?).
[ak4634] rev. 0.5 2007/10 - 29 - ext slave mode (pmpll bit = ?0?, m/s bit = ?0?) when pmpll bit is ?0?, the ak4634 becomes ext slave mode. master clock is input from the mcki pin, the internal pll circuit is not operated. this mode is compatible with i/f of the normal audio codec. the clocks required to operate are mcki (256fs, 512fs or 1024fs), fck (fs) and bick ( 32fs). the master clock (mcki) should be synchronized with fck. the phase between these clocks is not important. the input frequency of mcki is selected by fs1-0 bits. ( table 11 ) mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 x 0 0 256fs 7.35khz fs 48khz (default) 1 x 0 1 1024fs 7.35khz fs 13khz 2 x 1 0 512fs 7.35khz fs 26khz 3 x 1 1 256fs 7.35khz fs 48khz table 11. mcki frequency at ext slave mode (p mpll bit = ?0?, m/s bit = ?0?) (x: don?t care) external slave mode does not support mode 0 (dsp mode) of audio interface format. the s/n of the dac at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. the out-of-band noise can be improved by usi ng higher frequency of the master clock. ( table 12 , table 13 ) s/n (fs=8khz, 20khzlpf + a-weighted) mcki dac aout 256fs 84db 512fs 92db 1024fs 92db table 12. relationship between mc ki and s/n of aout and spk-amp output noise level (svdd=3.3v,fs=8khz, 20khzlpf + a-weighted) mcki sdti spk-amp 256fs -73dbv 512fs -86dbv 1024fs -88dbv table 13. relationship between mcki and output noise level of spk-amp the external clocks (mcki, bick and fck) should always be present whenever the adc or dac or spk or programmable filter is in operation (pmadc = pmdac = pm spk bit = pmpfil bits = ?1?). if these clocks are not provided, the ak4634 may draw excess current and it is not possible to operate properl y because utilizes dynamic refreshed logic internally. if the extern al clocks are not present, the adc, dac , spk and programmable filter should be in the power-down mode (pmadc = pmdac = pmspk bit = pmpfil bits = ?0?). ak4634 dsp or p mcki bick fck sdto sdti bclk fck sdti sdto mcko 1fs 32fs mclk 256fs, 512fs or 1024fs figure 23. ext slave mode
[ak4634] rev. 0.5 2007/10 - 30 - ext master mode (pmpll bit = ?0?, m/s bit = ?1?) the ak4634 becomes ext master mode by setting pmpll bit = ?0? and m/s bit = ?1?. master clock is input from the mcki pin, the internal pll circuit is not operated. the clock required to operate is mcki (256fs, 512fs or 1024fs). the input frequency of mcki is selected by fs1-0 bits ( table 14 ). the bick is selected among 32fs or 64fs, by bcko1-0 bits ( table 15 ). fck bit should be set to ?0?. mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 x 0 0 256fs 7.35khz fs 48khz (default) 1 x 0 1 1024fs 7.35khz fs 13khz 2 x 1 0 512fs 7.35khz fs 26khz 3 x 1 1 256fs 7.35khz fs 48khz table 14. mcki frequency at ext master mode (p mpll bit = ?0?, m/s bit = ?1?) (x: don?t care) external master mode does not support mode 0 (dsp mode) of audio interface format. mcki should always be present when ever the adc, dac, spk or programmabl e filter is in operation (pmadc = pmdac = pmspk bit = pmpfil bits = ?1?). if mcki is not provided, the ak4634 may draw excess current and it is not possible to operate properly because utili zes dynamic refreshed logic internally. if mcki is not present, the adc, dac, spk and programmable filter should be in the power-down mode (pmadc = pmdac = pmspk = pmpfil bits = ?0?). ak4634 dsp or p mcki bick fck sdto sdti bclk fck sdti sdto mcko 1fs 32fs, 64fs mclk 256fs, 512fs or 1024fs figure 24. ext master mode mode bcko1 bcko0 bick output frequency 0 0 0 n/a (default) 1 0 1 32fs 2 1 0 64fs 3 1 1 n/a table 15. bick output frequency at master mode (n/a: not available)
[ak4634] rev. 0.5 2007/10 - 31 - audio interface format four types of data formats are available a nd are selected by setting the dif1-0 bits. ( table 16 ) in all modes, the serial data is msb first, 2?s complement format. audio interface format s can be used in both master and slave modes. fck and bick are output from the ak4634 in master mode, but must be input to the ak4634 in slave mode. in mode 1-3, the sdto is clocked out on the falling edge of bick and the sdti is latched on the rising edge. mode dif1 dif0 sdto (adc) sdti (dac) bick figure 0 0 0 dsp mode dsp mode 16fs see table 17 1 0 1 msb justified msb justified 32fs figure 25 2 1 0 msb justified msb justified 32fs figure 26 (default) 3 1 1 i 2 s compatible i 2 s compatible 32fs figure 27 table 16. audio interface format in mode0 (dsp mode), the audio i/f timing is changed by bckp and msbs bits. when bckp bit is ?0?, sdto data is output by rising edge of bick, sdti data is latched by falling edge of bick. when bckp bit is ?1?, sdto data is output by falling edge of bick, sdti data is latched by rising edge of bick. msb data position of sdto and sdti can be shifted by msbs bit. the shifted period is a half of bick. msbs bit bckp bit audio interface format 0 0 figure 28 (default) 0 1 figure 29 1 0 figure 30 1 1 figure 31 table 17. audio interface format in mode 0 if 16-bit data, the output of adc, is converted to 8-bit data by removing lsb 8-bit, ? ? 1? at 16bit data is converted to ? ? 1? at 8-bit data. and when the dac playbacks this 8-bit data, ? ? 1? at 8-bit data will be converted to ? ? 256? at 16-bit data and this is a large offset. this offset can be removed by addi ng the offset of ?128? to 16-bit data before converting to 8-bit data. fck bick(32fs) sdto(o) 0 1 2 8 9 10 12 13 15 0 1 2 8 9 10 12 13 15 0 15 1 14 4 87 6 0 32 11 1 4 1 5 14 11 15 bick(64fs) sdto(o) 0 1 2 3 14 15 17 18 31 0 1 2 14 15 17 18 31 0 15 1 14 0 15 sdti(i) 10 15 14 15:msb, 0:lsb data 1/fs don?t care 2 1 13 don?t care 16 16 3 3 13 3 15 14 4 7 6 0 321 5 15 13 sdti(i) don?t care figure 25. mode 1 timing
[ak4634] rev. 0.5 2007/10 - 32 - fck bick(32fs) sdto(o) 0 1 2 8 9 10 12 13 15 0 1 2 8 9 10 12 13 15 0 15 1 14 4 87 6 0 32 11 1 4 1 5 14 11 15 13 bick(64fs) sdto(o) 0 1 2 3 14 15 17 18 31 0 1 2 14 14 15 17 18 31 0 15 1 14 0 15 sdti(i) 15:msb, 0:lsb data 1/fs don?t care 2 1 13 don?t care 16 16 3 13 15 14 2 1 13 0 15 sdti(i) 15 14 4 87 6 0 321 5 15 don?t care figure 26. mode 2 timing fck bick(32fs) sdto(o) 0 1 2 4 9 10 12 13 15 0 1 2 4 9 10 12 13 15 0 1 15 5 13 7 7 1 43 11 1 4 2 6 0 14 11 13 bick(64fs) sdto(o) 0 1 2 3 14 15 17 18 31 0 1 2 4 14 15 17 18 31 0 1 15 0 sdti(i) 15:msb, 0:lsb data 1/fs don?t care 2 1 14 don?t care 16 16 3 13 15 2 1 14 0 14 3 3 4 sdti(i) 15 5 13 7 1 432 6 0 14 figure 27. mode 3 timing
[ak4634] rev. 0.5 2007/10 - 33 - fck bick ( 16fs ) sdto(o) 15 0 1 8 8 9 11 12 14 15 0 1 8 8 9 11 12 14 15 0 0 15 5 88 7 1 43 10 13 2 6 0 15 5 887 1 4 3 2 6 13 10 0 2 14 14 2 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 6 0 14 14 sdti(i) bick ( 32fs ) sdto(o) 15 0 1 8 14 15 17 18 30 31 0 1 8 8 9 11 12 30 31 0 15 82 1 16 29 0 15 821 0 13 10 15:msb, 0:lsb 1/fs 2 14 14 2 15 2 1 0 15 8210 14 14 sdti(i) 1/fs don?t care don?t care figure 28. mode 0 timing (bckp = ?0?, msbs = ?0?) fck bick ( 16fs ) sdto(o) 15 0 1 8 8 9 11 12 14 15 0 1 8 8 9 11 12 14 15 0 0 15 5 8 8 7 1 43 10 13 2 6 0 15 5 887 1 4 3 2 6 13 10 0 2 14 14 2 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 6 0 14 14 sdti(i) bick ( 32fs ) sdto(o) 15 0 1 8 14 15 17 18 30 31 0 1 8 8 9 11 12 30 31 0 15 8 2 1 16 29 0 15 821 0 13 10 15:msb, 0:lsb 1/fs 2 14 14 2 15 2 1 0 15 8210 14 14 sdti(i) 1/fs don?t care don?t care figure 29. mode 0 timing (bckp = ?1?, msbs = ?0?)
[ak4634] rev. 0.5 2007/10 - 34 - fck bick ( 16fs ) sdto(o) 15 0 1 8 8 9 11 12 14 15 0 1 8 8 9 11 12 14 15 0 0 15 5 8 8 7 1 43 10 13 2 6 0 15 5 887 1 4 3 2 6 13 10 0 2 14 14 2 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 6 0 14 14 sdti(i) bick ( 32fs ) sdto(o) 15 0 1 8 14 15 17 18 30 31 0 1 8 8 9 11 12 30 31 0 15 8 2 1 16 29 0 15 821 0 13 10 15:msb, 0:lsb 1/fs 2 14 14 2 15 2 1 0 15 8210 14 14 sdti(i) 1/fs don?t care don?t care figure 30. mode 0 timing (bckp = ?0?, msbs = ?1?) fck bick ( 16fs ) sdto(o) 15 0 1 8 8 9 11 12 14 15 0 1 8 8 9 11 12 14 15 0 0 15 5 8 8 7 1 43 10 13 2 6 0 15 5 887 1 4 3 2 6 13 10 0 2 14 14 2 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 6 0 14 14 sdti(i) bick ( 32fs ) sdto(o) 15 0 1 8 14 15 17 18 30 31 0 1 8 8 9 11 12 30 31 0 15 8 2 1 16 29 0 15 821 0 13 10 15:msb, 0:lsb 1/fs 2 14 14 2 15 2 1 0 15 8210 14 14 sdti(i) 1/fs don?t care don?t care figure 31. mode 0 timing (bckp = ?1?, msbs = ?1?)
[ak4634] rev. 0.5 2007/10 - 35 - system reset when power-up, the pdn pin should be ?l? and change to ?h ? after all power are supplied. ?l? time of 150ns or more is needed to reset in the ak4634. the adc enters an initialization cycle when the pmadc bit is changed from ?0? to ?1?. the initialization cycle time is 1059/fs, or 133ms@fs = 8khz. during the initia lization cycle, the adc digital data out puts of both channels are forced to a 2's compliment, ?0?. the adc output re flects the analog input signal after the in itialization cycle is complete. the dac does not require an initialization cycle. (note) off-set occurs in the initial data depending on th e conditions of a microphone and cut-off frequency of hpf. when off-set becomes a problem, lengthen initialization time of adc as adrst bit = ?0? or do not use initial output data of adc. init cycle adrst bit cycle fs = 8khz fs = 16khz fs = 48khz 0 1059/fs 132.4ms 66.2ms 22.1ms 1 291/fs 36.4ms 18.2ms 6.1ms table 18 initialization cycle of adc thermal shut down when the internal device temperature rises up irregularly (e.g. output pins of speaker amplifier are shortened), the ak4634 is powered down automatically and then thdet bit becomes ?1?. the powered-down speaker amplifier do not return to normal operation unless spk-amp blocks of the ak4634 are reset by the pdn pin ?l?. the device status can be monitored by thdet bit. mic/line input selector the ak4634 has an input selector. when mdif bit is ?0?, lin bit selects the mic pin or the lin pin. when mdif bit is ?1?, full-differential input is available. mdif bit lin bit input circuit input pin 0 0 single-end mic pin (default) 0 1 single-end lin pin 1 x differential micp/micn pin table 19. input select (x: don?t care) figure 32 input selector mic/micp pin a dc lin/micn pin lin bit mdif bit ak4634
[ak4634] rev. 0.5 2007/10 - 36 - micp pin micnpin mpi pin ak4634 mic-amp 1k 1k hpf a/d mic-power bick pin fck pin stdo pin audio i/f figure 33. mic differential input circuit mic gain amplifier the ak4634 has a gain amplifier for microphone input. these gains are selected by the mgain3-0 bit. the typical input impedance is 30k . mgain3 bit mgain2 bit mgain1 bit mgain0 bit input gain 0 0 0 0 0db 0 0 0 1 +20db (default) 0 0 1 0 +26db 0 0 1 1 +32db 0 1 0 0 +10db 0 1 0 1 +17db 0 1 1 0 +23db 0 1 1 1 +29db 1 0 0 0 +3db 1 0 0 1 +6db others n/a table 20. input gain mic power the mpi pin supplies power for the microphone. this output voltage is proportional to 0.8 x avdd typically and the load resistance is minimum 2k . any capacitor must not be connect ed to the mpi pin, directly. ( figure 34 ) mic pin mpi pin ak4634 mic-amp 2k hpf a/d mic-power bick pin fck pin stdo pin audio i/f figure 34. mic block circuit
[ak4634] rev. 0.5 2007/10 - 37 - digital block the digital block consists of block diagram as shown in figure 35 . the ak4634 can choose various signal processing on a recording path or a playback path by setting adcpf bit, pfdac bit and pfsdo bit. ( figure 35 - figure 38 , table 21 ) dac 1st order hpf adc alc (volume) datt smute sdti a dcpf bit ?1? ?0? 5 band eq 1st order hpf pfdac bit ?1? ?0? pfsdo bit ?0? ?1? sdto hpf bit eq5-1 bits hpfad bit pmpfil bit pmdac bit pmadc bit 1st order lpf lpf bit (1) adc: include the digital filter (lpf) for adc as shown in ?filter chracteristics?. (2) dac: include the digital filter (lpf) for dac as shown in ?filter chracteristics?. (3) hpf: high pass filter. applicable to use as wind-noise reduction filter. (see ? digital programmable filter circuit ?.) (4) lpf: low pass filter (see ? digital programmable filter circuit ?.) (5) 5-band eq: applicable to use as equalizer or notch filter. (see ? digital programmable filter circuit ?.) (6) alc: input digital volume with alc function. (see ? input digital volume ? and ? alc operation ?.) (7) datt: 4-step digital volume for recording path. (see ? output digital volume 2 ?) (8) smute: soft mute. (see ? soft mute ?.) figure 35. digital block path select
[ak4634] rev. 0.5 2007/10 - 38 - mode adcpf bit pfdac bit pfsdo bit figure recording mode 1 0 1 figure 36 reproduction mode 0 1 0 figure 37 loop back mode 1 1 1 figure 38 table 21 recording reproduction mode dac 2nd order hpf adc 5 band eq alc (volume) datt smute 1st order lpf figure 36. path at recording mode (default) dac 1st order hpf adc datt smute alc (volume) 5 band eq 1st order hpf 1st order lpf figure 37. path at playback mode dac 2nd order hpf adc 5 band eq alc (volume) datt smute 1st order lpf figure 38. path at recording & playback mode
[ak4634] rev. 0.5 2007/10 - 39 - digital programmable filter circuit the ak4634 has 2 steps of 1 st order hpf, 1 st order lpf and 5-band equalizer built-in in a recording path and a playback path. (1) high pass filter (hpf) normally, this hpf is used as a wind-noise reduction filter. this is composed with 2 steps of 1st order hpf. the coefficient of both hpf is the same and set by f1a13-0 bits and f1b13-0 bits. hpfad bit controls on/off of the 1st step hpf and hpf bit controls on/off of the 2nd step hpf. when the hpf is off, the audio data passes this block by 0db gain. the coefficient should be set when hpfad = hpf bits = ?0? or pmadc = pmpfil bits = ?0?. fs : sampling frequency fc : cut-off frequency register setting ( note 32 ) hpf: f1a[13:0] bits = a, f1b[13:0] bits = b (msb = f1a13, f1b13; lsb = f1a0, f1b0) a = 1 1 + tan ( fc/fs) b = 1 ? tan ( fc/fs) 1 + tan ( fc/fs) , the cut-off frequency should be set as below. fc/fs ? 0.0001 (fc min = 1.6hz at 16khz) (2) low pass filter(lpf) this is composed with 1st order lpf. f2a13-0 bits and f2b 13-0 bits set the coefficient of lpf. lpf bit controls on/off of the lpf. when the lpf is off, the audio data passes this block by 0db gain. the coefficient should be set when lpf bit = ?0? or pmpfil bits = ?0?. fs : sampling frequency fc : cut-off frequency register setting ( note 32 ) lpf: f2a[13:0] bits =a, f2b[13:0] bits =b (msb=f2a13, f1b13; lsb=f2a0, f2b0) a = 1 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , the cut-off frequency should be set as below. fc/fs ? ? 0.05 (fc min = 2205hz at 44.1khz)
[ak4634] rev. 0.5 2007/10 - 40 - (3) 5-band equalizer this block can be used as equalizer or notch filter. on/ off 5-band equalizer (eq1, eq2, eq3, eq4 and eq5) can be controlled independently by eq1, eq2, eq3, eq4 and eq5 bits . when equalizer is off, the audio data passes this block by 0db gain. e1a15-0, e1b15-0 and e1c15-0 bits set the coefficient of eq1. e2a15-0, e2b15-0 and e2c15-0 bits set the coefficient of eq2. e3a15-0, e3b15-0 and e3c15-0 bits set the coefficient of eq3. e4a15-0, e4b15-0 and e4c15-0 bits set the coefficient of eq4. e5a15-0, e5b15-0 and e5c 15-0 bits set the coefficient of eq5. each eqx coefficient setting must be made when eqx bit (corresponding bit to eqx) is ?0? or pmpfil bit is ?0?. fs : the sampling frequency fo 1 ~ fo 5 : the center frequency fb 1 ~ fb 5 : the band width where the gain is 3db different from center frequency k 1 ~ k 5 : the gain ( -1 k n < ?3 ) register setting ( note 32 ) eq1: e1a[15:0] bits =a 1 , e1b[15:0] bits =b 1 , e1c[15:0] bits =c 1 eq2: e2a[15:0] bits =a 2 , e2b[15:0] bits =b 2 , e2c[15:0] bits =c 2 eq3: e3a[15:0] bits =a 3 , e3b[15:0] bits =b 3 , e3c[15:0] bits =c 3 eq4: e4a[15:0] bits =a 4 , e4b[15:0] bits =b 4 , e4c[15:0] bits =c 4 eq5: e5a[15:0] bits =a 5 , e5b[15:0] bits =b 5 , e5c[15:0] bits =c 5 (msb=e1a15, e1b15, e1c15, e2a15, e2b15, e2c15, e3a15, e3b15, e3c15, e4a15, e4b15, e4c15, e5a15, e5b15, e5c15 ; lsb= e1a0, e1b0, e1c0, e2a0, e2b0, e2c0, e3a0, e3b0, e3c0, e4a0, e4b0, e4c0, e5a0, e5b0, e5c0) a n = k n x tan ( fb n /fs) 1 + tan ( fb n /fs) b n = cos(2 fo n /fs) x 2 1 + tan ( fb n /fs) , c n = 1 ? tan ( fb n /fs) 1 + tan ( fb n /fs) , (n = 1, 2, 3, 4, 5) the center frequency should be set as below fo n / fs < 0.497 when gain of k is set to ? ? 1?, the equalizer becomes notch filter. when it is used as notch filter, central frequency of a real notch filter deviates from the above -mentioned calculation, if its central fre quency of each band is near. the control soft that is attached to the evaluation board has a function that revises a gap of frequency, and calculates the coefficient. when its central frequency of each band is near, revise the central frequency and confirm the frequency response. note 32. [translation the filter coefficient calculate d by the equations above fro m real number to binary code (2?s complement)] x = (real number of filter coefficient calculated by the equations above) x 2 13 x should be rounded to integer, and then should be translated to binary code (2?s complement). msb of each filter coefficient se tting register is sine bit.
[ak4634] rev. 0.5 2007/10 - 41 - input digital volume (manual mode) when adcpf bit = ?1? and alc1 bit = ?0?, alc block becomes an input digital volume (manual mode). the digital volume?s gain is set by ivol7-0 bits as shown in table 22 . the ivol value is changed at zero cross or zero cross time out. the zero crossing timeout period is set by ztm1-0 bits. ivol7-0bits gain(0db) step f1h +36.0 f0h +35.625 efh +35.25 : : 92h +0.375 91h 0.0 (default) 90h -0.375 : : 0.375db 2h -53.625 1h -54.0 0h mute table 22. input digital volume setting when writing to the ivol7-0 bits conti nually, the control register should be written in an interval more than zero crossing timeout. if not, zero cro ssing counter could be reset at each time and vol ume is not be changed. however, it could be ignored when writing the same register value as the last time. at this time, zero crossing counter is not reset, so it can be written in an interval less than zero crossing timeout.
[ak4634] rev. 0.5 2007/10 - 42 - output digital volume (manual mode) when adcpf bit = ?0? and alc2 bit = ?0?, alc block become an output digital volume (manual mode). the digital volume?s gain is set by ovol7-0 bits as shown in table 23 . the ovol7-0 bits value are re flected to this output volume at zero cross or zero cross time out. the zero crossing timeout period is set by ztm1-0 bits. ovol7-0bits gain(0db) step f1h +36.0 f0h +35.625 efh +35.25 : : 92h +0.375 91h 0.0 (default) 90h -0.375 : : 0.375db 2h -53.625 1h -54.0 0h mute table 23 output digital volume setting when writing to the ovol7-0 bits continually, the control re gister should be written by an interval more than zero crossing timeout. if not, zero cro ssing counter could be reset at each time and volume is not be cha nged. however, it could be ignored when writing a same regist er value as the last time. at this time, zero crossing c ounter is not reset, so it can be written by an interval less than zero crossing timeout. output digital volume2 the ak4634 has 4 steps output volume in addition to the volume setting by ovol7- 0 bits. this volume is set by datt1-0 bits as shown in table 24 . datt1-0bits gain(0db) step 0h 0.0 (default) 1h -6.0 2h -12.0 6.0db 3h -18.1 table 24. output digital volume2 setting
[ak4634] rev. 0.5 2007/10 - 43 - alc operation alc operation works in alc block. when adcpf bit = ?1?, alc operation is enable for recording path. when adcpf bit = ?0?, alc operation is enable for playback path. the on/off of alc operation for recording is controlled by alc1 bit and the on/off of alc operation for playback is controlled by alc2 bit. 1. alc limiter operation when the alc limiter is enabled, and output exceeds the alc limiter detection level ( table 25 ), the volume value is attenuated by the amount defined in lmat1-0 bits ( table 26 ) automatically. when the zelmn bit = ?0? (zero crossing detection valid), the vol value is ch anged by alc limiter operation at the zero crossing point or zero crossing timeout. zero crossing timeout period is set by ztm1-0 bit that in common with alc recovery zero crossing timeout period?s setting ( table 27 ).at lfst bit = ?1?, vol value is attenuated 1step immediately (period: 1/fs) when output level is over fs(digital full scale). when the zelmn bit = ?1? (zero crossing de tection invalid), vol value is change d immediately (period: 1/fs) by alc limiter operation. the attenuation for limiter operation is fixe d to 1 step and not controlled by setting lmat1-0 bits. after finishing the attenuate operation, if alc bit does not change to ?0?, the operation repeats when the output signal level exceeds the alc limiter detection level. lmth1 lmth0 alc limiter detection level alc recovery waiting counter reset level 0 0 alc output ? 2.5dbfs ? 2.5dbfs > alc output ? 4.1dbfs 0 1 alc output ? 4.1dbfs ? 4.1dbfs > alc output ? 6.0dbfs (default) 1 0 alc output ? 6.0dbfs ? 6.0dbfs > alc output ? 8.5dbfs 1 1 alc output ? 8.5dbfs ? 8.5dbfs > alc output ? 12dbfs table 25. alc limiter detection level / recovery waiting counter reset level alc1 limiter att step lmat1 lmat0 alc1 output lmth alc1 output fs alc1 output fs + 6db alc1 output fs + 12db 0 0 1 1 1 1 (default) 0 1 2 2 2 2 1 0 2 4 4 8 1 1 1 2 4 8 table 26. alc limiter att step setting zero crossing timeout period ztm1 ztm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms (default) 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 27. alc zero crossing timeout period setting
[ak4634] rev. 0.5 2007/10 - 44 - 2. alc recovery operation the alc recovery operation waits for the wtm2-0 bits ( table 28 ) to be set after completing the alc limiter operation. if the input signal does not exceed ?alc r ecovery waiting counter reset level? ( table 25 ) during the wait time, the alc recovery operation is executed. the vol value is automatically incremented by rgain1-0 bits ( table 29 ) up to the set reference level ( table 30 , table 31 ) with zero crossing detection which timeout period is set by ztm1-0 bits ( table 27 ). the alc recovery operation is executed in a period set by wtm2-0 bits. for example, when the current vol value is 30h and rgain1-0 bits are set to ?01?(2 steps), vol is changed to 32h by the auto limiter operation and then the input signal level is gained by 0.75db (=0.375db x 2). when the vol value exceeds the reference level (iref7-0 or oref 5-0), the vol values are not increased. when ?alc recovery waiting counter reset level (lmth1-0) output signal < alc limiter detection level (lmth1-0)? during the alc recovery operation, the waiting timer of alc recovery operation is reset. when ?alc recovery waiting counter reset level (lmth1-0) > output signal?, the waiting timer of alc recovery operation starts. the alc operation corresponds to the impulse noise. when the impulse noise is input, the alc recovery operation becomes faster than a normal recovery operation. when larg e noise is input to microphone instantaneously, the quality of small level in the large noise can be improved by this fast r ecovery operation. the speed of first recovery operation is set by rfst1-0 bits ( table 32 ). alc recovery operation waiting period wtm2 wtm1 wtm0 8khz 16khz 44.1khz 0 0 0 128/fs 16ms 8ms 2.9ms (default) 0 0 1 256/fs 32ms 16ms 5.8ms 0 1 0 512/fs 64ms 32ms 11.6ms 0 1 1 1024/fs 128ms 64ms 23.2ms 1 0 0 2048/fs 256ms 128ms 46.4ms 1 0 1 4096/fs 512ms 256ms 92.9ms 1 1 0 8192/fs 1024ms 512ms 185.8ms 1 1 1 16384/fs 2048ms 1024ms 371.5ms table 28. alc recovery operation waiting period rgain1 rgain0 gain step 0 0 1 0.375db (default) 0 1 2 0.750db 1 0 3 1.125db 1 1 4 1.500db table 29. alc recovery gain step
[ak4634] rev. 0.5 2007/10 - 45 - iref7-0bits gain(0db) step f1h +36.0 f0h +35.625 efh +35.25 : : c5h +19.5 (default) : : 92h +0.375 91h 0.0 90h -0.375 : : 0.375db 2h -53.625 1h -54.0 0h mute table 30. reference level at alc recovery operation for recoding oref5-0bits gain(0db) step 3ch +36.0 3bh +34.5 3ah +33.0 : : 28h +6.0 (default) : : 25h +1.5 24h 0.0 23h -1.5 : : 1.5db 2h -51.0 1h -52.5 0h -54.0 table 31. reference level at alc recovery operation for playback rfst1 bit rfst0 bit recovery speed 0 0 4 times (default) 0 1 8 times 1 0 16times 1 1 n/a table 32. first recovery speed setting (n/a: not available)
[ak4634] rev. 0.5 2007/10 - 46 - 3. the volume at the alc operation the current volume value at the alc operati on is reflected by vol7-0 bits. it is en able to check the current volume value by reading the register value of vol7-0 bits. this function is available only at the time of 3-wire mode. the volume value at the alc operation can not be read in i 2 c mode. vol7-0bits gain(0db) f1h +36.0 f0h +35.625 efh +35.25 : : c5h +19.5 : : 92h +0.375 91h 0.0 90h ? 0.375 : : 2h ? 53.625 1h ? 54.0 0h mute table 33. value of vol7-0 bits 4. example of the alc operati on for recording operation table 34 shows the examples of the alc setting for mic recording. fs=8khz fs=16khz register name comment data operation data operation lmth1-0 limiter detection level 01 ? 4.1dbfs 01 ? 4.1dbfs zelm limiter zero crossing det ection 0 enable 0 enable ztm1-0 zero crossing timeout period 00 16ms 01 16ms wtm2-0 recovery waiting period *wtm1-0 bits should be more than or equal to ztm1-0 bits 000 16ms 001 16ms iref7-0 maximum gain at recovery operation c5h 19.5db c5h 19.5db ivol7-0 gain of ivol c5h 19.5db c5h 19.5db lmat1-0 limiter att step 00 1step 00 1step lfst fast limiter operation 1 on 1 on rgain1-0 recovery gain step 00 1 step 00 1 step alc1 alc enable 1 enable 1 enable frsl1-0 speed of fast recovery 00 4 times 00 4times table 34. example of the alc setting (recording)
[ak4634] rev. 0.5 2007/10 - 47 - 5. example of alc for playback operation table 35 shows the example of the alc setting for playback. fs=8khz fs=16khz register name comment data operation data operation lmth1-0 limiter detection level 01 ? 4.1dbfs 01 ? 4.1dbfs zelm limiter zero crossing det ection 0 enable 0 enable ztm1-0 zero crossing timeout period 00 16ms 01 16ms wtm2-0 recovery waiting period *wtm1-0 bits should be more than or equal to ztm1-0 bits 000 16ms 001 16ms oref5-0 maximum gain at rec overy operation 28 +6db 28 +6db ovol7-0 gain of ivol 91 0db 91 0db lfst fast limiter operation 1 on 1 on lmat1-0 limiter att step 00 1step 00 1step rgain1-0 recovery gain step 00 1 step 00 1 step alc2 alc enable 1 enable 1 enable frsl1-0 speed of fast recovery 00 4 times 00 4 times table 35. examples of the alc setting (play back)
[ak4634] rev. 0.5 2007/10 - 48 - the following registers must not be changed during the alc operation. these bits should be changed, after the alc operation is finished by alc1 bit = alc2 bit = ?0? or pmpfil bit = ?0?. after alc1 bit and alc2 bit set to ?0? or pmpfil bit sets to ?0?, when alc is restarted, the waiting time of zero crossing timeout is not needed. lmth1-0, lmat1-0, wtm2-0, ztm1-0, rgain1 -0, iref7-0/oref7-0, zelm, rfst1-0, lfst manual mode wr (ztm1-0, wtm2-0) wr (iref7-0/oref5-0) wr (ivol7-0/ovol7-0) wr (lfst,lmat1-0, rgain0, zelmn, lmth0) wr ( alc1= ?1? ) example: limiter = zero crossing enable recovery cycle = 16ms@8khz limiter and recovery step = 1 lfst = 1 maximum gain = +19.5db limiter detection level = ? 4.1dbfs alc1 bit = ?1? (1) addr=06h, data=00h (2) addr=08h, data=c5h (5) addr=07h, data=a1h (3) addr=09h, data=c5h alc operation wr (rgain1, lmth1,rfst1-0) (4) addr=0bh, data=28h *2 *1 note : wr : write *1: the value of volume at starting should be the same or smaller than ref?s. *2: when setting alc1 bit or alc2 bit to ?0?, the operation is shifted to manual mode after passing the zero crossing time set by ztm1-0 bits. figure 39. registers set-up sequence at the alc operation
[ak4634] rev. 0.5 2007/10 - 49 - softmute soft mute operation is performed in the digital input domain. when the smute bit changes to ?1?, the input signal is attenuated by ? (?0?) during the cycle of 245/fs (31msec@fs=8khz). when the smute bit is returned to ?0?, the mute is cancelled and the input attenuation gradually changes to 0db during the cycle of 245/fs (31msec@fs=8khz). if the soft mute is cancelled within the cycle of 245/fs (31msec@fs=8kh z), the attenuation is discontinued and returned to 0db. the soft mute for playback operation is effective for changing the signal source without stopping the signal transmission. smute bit a ttenuation 245/fs 0db - 245/fs gd gd (1) (2) (3) a nalog output figure 40. soft mute function (1) the input signal is attenuated by ? (?0?) during the cycle of 245/fs (31msec@fs=8khz). (2) analog output corresponding to digital input has the group delay (gd). (3) if the soft mute is cancelled within the cycle of 245/fs ( 31msec@fs=8khz), the attenuation is discounted and returned to 0db within the same cycle.
[ak4634] rev. 0.5 2007/10 - 50 - mono line output (aout pin) a signal of dac is output from th e aout pin. when the daca bit is ?0?, this output is off. when the lovl bit is ?1?, this gain changes to +2db. the load resistance is 10k (min). when pmao bit is ?0? and aopsn bit is ?0?, the mono line output enters power-down and is pulled down by 100 (typ). if pmao bit is controlled at aops bit = ?1?, pop noise will be reduced at power-up and down. th en, this line should be pulled down by 20k of resister after c-coupling shown in figure 41 . this rising and falling time is max 300 ms at c = 1.0 f . when pmao bit is ?1? and aops bit is ?0?, the mono line output enters power-up state. lovl bits gain 0 0db (default) 1 +2db table 36. mono line output volume setting aout 1 f 220 20k figure 41. aout external circuit when using pop reduction function aout control sequence in case of using pop reduction circuit p m a o bit a ops bit a out pin (1) (2) normal output (3) (4) (5) (6) 300 m s 300 m s figure 42. mono line output control sequence when using pop reduction function (1) set aops bit = ?1?. mono line output enters the power-save mode. (2) set pmao bit = ?1?. mono line output exits the power-down mode. aout pin rises up to vcom voltage. rise time is 200ms (max 300ms) at c=1 f. (3) set aops bit = ?0? after aout pin rises up. mono line output exits the power-save mode. mono line output is enabled. (4) set aops bit = ?1?. mono line output enters power-save mode. (5) set pmao bit = ?1?. mono line output enters power-down mode. aout pin falls down to vss1. fall time is 200ms (max 300ms) at c=1 f. (6) set aops bit = ?0? after aout pin falls down. mono line output exits the power-save mode.
[ak4634] rev. 0.5 2007/10 - 51 - speaker output ak4634 has a mono class-d speaker-amp. power supply for speaker-amp(svdd) can be set from 2.2v up to 4.0v. the speaker is mono and btl output, and can drive dynamic speaker and piezo speaker w ithout lpf (filter-less). this speaker can output 400w@8 ? at svdd = 3.3v, spkg bit = ?0?. this gain is set by spkg bit ( table 37 ). the output level of speaker amp is depended on voltage of svdd and spkg bit. spkg bit gain 0 0db 1 +2db ( note 33 ) note 33. the signals more than -2dbfs clip. table 37. spk- amp gain the power up/down speaker amp is controlled by pmspk bit. when pmspk bit is ?0?, the spp and spn pins output vss3 level. also on/off of speaker am p is controlled by spoute bit. when sp oute bit is ?0?, the spp and spn pins are in vss3-state forcibly. when the outputting from dac to speaker, pmdac bit should be set to ?1?. follow the following sequence. pmspk bit s p o u t e bit spp pin n orm al o utput spn pin normal output figure 43. power-up/power-down timing for speaker-amp
[ak4634] rev. 0.5 2007/10 - 52 - when a piezo speaker is used , resistances more than 10 should be connected between th e spp/spn pins and speaker in series, respectively, as shown in figure 44 . zener diodes should be connected between speaker and gnd as shown in figure 44 , in order to protect spk-amp of the ak4634 from the power that is the piezo speaker output when the speaker is pressured. zener diodes of the fo llowing zener voltage should be used. 92% of svdd zener voltage of zener diodo (zd of figure 44 ) svdd+0.3v ex) in case of svdd = 3.8v :3.5v zd 4.1v for example, zener diode which zener voltage is 3.9v(min 3.7v, max 4.1v) can be used. spp spk-amp spn 10 10 zd zd figure 44. circuit of speaker output (using a piezo speaker)
[ak4634] rev. 0.5 2007/10 - 53 - beep generate the ak4634 generates and output square wave from speaker amp. after out putting the signal during the time set by bpon6-0 bits, the ak4634 stops the output signal during the time set by bpoff6-0 bits ( figure 46 ). the repeat count is set by bptm6-0 bit, and the output level is set by bplvl2-0 bits. when bpcnt bit is ?0?, if bpout bit is written ?1?, the ak4634 outputs the beep for the times of repeat count. when the output finish, bpout bit is set to ?0? automatically. when bpcnt bit is set to ?1?, it outputs the beep in succession regardless of repeat count, on-time and off-time. < setting parameter > 1) output frequency ( table 38 ~ table 40 ) 2) on time ( table 41 ) 3) off time ( table 42 ) 4) repeat count ( table 43 ) 5) output level ( table 44 ) bpfr1-0, bpon7-0, bpoff7-0, bptm6-0 and bplv l3-0 bits should be set when bpout =bpcnt = ?0?. bpcnt bit is given priority in bpou t bit. when bpout bit be set to ?1 ?, if bpcnt bit is set to ?0?, bpout bit is set to ?0? forcibly. dac line out am p beep generator class-d spk-am p datt2 smute lpf figure 45. beep signal output path beep output on time off time repeat count figure 46. beep output
[ak4634] rev. 0.5 2007/10 - 54 - output frequency of beep generator [hz] bpfr1-0 bit fs = 48khz system ( note 34 ) fs = 44.1khz system ( note 35 ) 00 4000 4009 (default) 01 2000 2005 10 1000 1002 11 n/a note 34. sampling frequency is 8khz, 16khz, 32khz or 48khz. note 35. sampling frequency is 11.025khz, 22.05khz or 44.1khz. table 38. beep signal frequency (pll master/slave m ode: reference clock: mcki) (n/a: not available) output frequency of beep generator [hz] bpfr1-0 bit fs3-2 bits = ?00? fs3-2 bits = ?01? fs3-2 bits = ?10? 00 fs/2.75 fs/5.5 fs/11 (default) 01 fs/5.5 fs/11 fs/22 10 fs/11 fs/22 fs/44 11 n/a table 39. beep signal frequency ( pll slave mode: re ference clock : fck/bick) (n/a: not available) output frequency of beep generator [hz] bpfr1-0 bit fs1-0 bits = ?00? fs1-0 bits = ? 01? fs1-0 bits = ?10? fs1-0 bits = ?11? 00 fs/11 fs/2.75 fs/55 fs/11 (default) 01 fs/22 fs/5.5 fs/11 fs/22 10 fs/44 fs/11 fs/22 fs/44 11 n/a table 40. beep signal frequency (ext slave/master mode) (n/a: not available) on time of beep generator [msec] step [msec] bpon7-0 bit fs = 48khz system ( note 34 ) fs = 44.1khz system ( note 35 ) fs = 48khz system ( note 34 ) fs = 44.1khz system ( note 35 ) 0h 8.0 7.98 8.0 7.98 (default) 1h 16.0 15.86 2h 24.0 23.95 3h 32.0 31.93 4h 40.0 39.9 : : : fdh 2032 2027.3 feh 2040 2035.3 ffh 2048 2043.4 note 34. sampling frequency is 8khz, 16khz, 32khz or 48khz. note 35. sampling frequency is 11.025khz, 22.05khz or 44.1khz. table 41. beep output on-time (pll master/slave mode reference clock: mcki)
[ak4634] rev. 0.5 2007/10 - 55 - off time of beep generator [msec] step [msec] bpoff7-0 bit fs = 48khz system ( note 34 ) fs = 44.1khz system ( note 35 ) fs = 48khz system ( note 34 ) fs = 44.1khz system ( note 35 ) 0h 8.0 7.98 8.0 7.98 (default) 1h 16.0 15.86 2h 24.0 23.95 3h 32.0 31.93 4h 40.0 39.9 : : : fdh 2032 2027.3 feh 2040 2035.3 ffh 2048 2043.4 note 34. sampling frequency is 8khz, 16khz, 32khz or 48khz. note 35. sampling frequency is 11.025khz, 22.05khz or 44.1khz. table 42. beep output off-time (pll master/slave mode reference clock: mcki) bptm6-0 bit repeat count 0h 1 (default) 1h 2 2h 3 3h : : 125 7dh 126 7eh 127 7fh 128 table 43. beep output repeat count bplvl3-0 bit beep output level step 0h 0db (default) 1h ? 3db 2h ? 6db 3h ? 9db 4h ? 12db 3db 5h ? 18db 6h ? 24db 7h ? 30db 6db note 36. power supply is 3.3v note 37. beep output amplitude as 0db setting is 4.4vpp@ load resistance = 8 ? + 10h, svdd=3.3v table 44. beep output level
[ak4634] rev. 0.5 2007/10 - 56 - serial control interface (1) 3-wire serial control mode (i2c pin = ?l?) internal registers may be written and r ead by using the 3-wire p interface pi ns (csn, cclk and cdtio). the data on this interface consists of read/write, register address (msb fi rst, 7bits) and control data (m sb first, 8bits). address and data is clocked in on the rising edge of cclk and data is clocked out on the falling edge. data writing is valid on the rising edge of the 16th cclk after the fa lling edge of csn. csn should be set to ?h? every after a data writing for each address. in reading operation, the cdtio pin changes to output mode at the falling edge of 8th cclk and outputs d7-d0. the output finishes on the rising edge of csn. however this reading function is available only at read bit = ?1?. when read bit = ?0?, the cdtio pin stay s as hi-z even after the falling edge of 8th cclk. the cdtio pin is placed in a hi-z state except outputting data at read operation mode. the clock speed of cclk is 5mhz (max). the value of internal registers is initialized at the pdn pin = ?l?. note 38. it is available for reading the address 00h ~ 11h, 20h ~ 24h and 30h. when reading the address 12h ~ 1fh, 25h ~ 2f and 31h ~ 4fh, the register values are invalid. csn cclk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cdtio a6 a5 a2 a3 a1 a0 a4 d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w: read/write (?1?: write, ?0?: read) a6-a0: register address d7-d0: control data clock, ?h? or ?l? clock, ?h? or ?l? ?h? or ?l? ?h? or ?l? figure 47. serial control i/f timing
[ak4634] rev. 0.5 2007/10 - 57 - (2) i 2 c-bus control mode (i2c pin = ?h?) the ak4634 supports the fast-mode i 2 c-bus (max: 400khz). pull-up resistors at sda and scl pins should be connected to (dvdd+0.3)v or less voltage. (2)-1. write operations figure 48 shows the data transfer sequence for the i 2 c-bus mode. all commands are pr eceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition ( figure 54 ). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit that is a data direction bit (r/w). the most significant seven bits of the slave address are fixed as ?0010010? ( figure 49 ). if the slave address matches that of the ak4634, the ak4634 generates an acknowledge and the operation is executed. the master must generate the acknowledge-related clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 55 ). a r/w bit value of ?1? indicates th at the read operation is to be execu ted. a ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the ak4634. the format is msb first, and those most significant 1-bits are fixed to zeros ( figure 50 ). the data after the second byte contains control data. the format is msb first, 8bits ( figure 51 ). the ak4634 generates an acknowledge after each by te is received. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition ( figure 54 ). the ak4634 can perform more than one by te write operation per sequence. after receipt of the third byte the ak4634 generates an acknowledge and awaits the next data. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after r eceiving each data packet the inte rnal 6-bit address counter is incremented by one, and the next data is automatically taken into the next addr ess. if the address exceeds 4fh prior to generating a stop condition, the address counter will ?roll over? to 00h and th e previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. the high or low state of the data line can only change when the cloc k signal on the scl line is low ( figure 56 ) except for the start and stop conditions. sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 48. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 1 0 r/w figure 49. the first byte 0 a6 a5 a4 a3 a2 a1 a0 figure 50. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 51. byte structure after the second byte
[ak4634] rev. 0.5 2007/10 - 58 - (2)-2. read operations set the r/w bit = ?1? for read operation of the ak4634. after transmission of data, the master can read the next address?s data by generating an acknowledge instead of terminating the write cy cle after the receipt of the first data word. after receiving each data packet the inte rnal 6-bit address counter is increm ented by one, and the next data is automatically taken into the next address. if the address exceeds 4fh prior to generating a stop condition, the address counter will ?roll over? to 00h and the data of 00h will be read out. note 38. it is available for reading the address 00h ~ 11h, 20h ~ 24h and 30h. when reading the address 12h ~ 1fh, 25h ~ 2f and 31h ~ 4fh, the register values are invalid. the ak4634 supports two basic read operations: current address read and random address read. (2)-2-1. current address read the ak4634 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) were to address n, the next current read operation would access data from the address n+1. after receipt of the sl ave address with r/w bit ?1 ?, the ak4634 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master doe s not generate an acknowledge but inst ead generates a stop condition, the ak4634 ceases the transmission. sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) n a c k p s t o p data(n) m a s t e r m a s t e r m a s t e r m a s t e r m a s t e r figure 52. current address read (2)-2-2. random address read the random read operation allows the master to access any memo ry location at random. prior to issuing the slave address with the r/w bit ?1?, the master must first perform a ?dummy? write operation. th e master issues a start request, a slave address (r/w bit = ?0?) and then the register address to read. after the register address is acknowledged, the master immediately reissues the start request and the slave address with the r/w bit set to ?1?. the ak4634 then generates an acknowledge, 1 byte of data and increments the internal a ddress counter by 1. if the master does not generate an acknowledge but instead generates a stop c ondition, the ak4634 ceases the transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k n a c k m a s t e r m a s t e r m a s t e r m a s t e r figure 53. random address read
[ak4634] rev. 0.5 2007/10 - 59 - scl sda stop condition start condition s p figure 54. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 55. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 56. bit transfer on the i 2 c-bus
[ak4634] rev. 0.5 2007/10 - 60 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 pmpfil pmvcm 0 pmspk pmao pmdac 0 pmadc 01h power management 2 0 0 0 0 m/s 0 mcko pmpll 02h signal select 1 spoute 0 dacs daca mgain3 pmmp mgain2 mgain0 03h signal select 2 pfsdo aops mgain1 0 spkg 0 pfdac adcpf 04h mode control 1 pll3 pll2 pll1 pll0 bcko1 bcko0 dif1 dif0 05h mode control 2 adrst fcko fs3 msbs bckp fs2 fs1 fs0 06h timer select 0 wtm2 ztm 1 ztm0 wtm1 wtm0 rfst1 rfst0 07h alc mode control 1 lfst alc2 alc1 zelmn lmat1 lmat0 rgain0 lmth0 08h alc mode control 2 iref7 iref6 iref5 iref4 iref3 iref2 iref1 iref0 09h digital volume control ivol7 ivol6 ivol5 ivol4 ivol 3 ivol2 ivol1 ivol0 0ah digital volume control ovol 7 ovol6 ovol5 ovol4 ovol 3 ovol2 ovol1 ovol0 0bh alc mode control 3 rgain1 lmth1 oref5 oref4 oref3 oref2 oref1 oref0 0ch reserved 0 0 0 0 0 0 1 0 0dh alc level vol7 vol6 vol 5 vol4 vol3 vol2 vol1 vol0 0eh signal select 3 datt1 datt0 smute mdif 1 0 1 read 0fh thermal shutdown thdet 0 0 0 0 0 0 0 10h signal select 4 0 lovl 0 0 0 0 lin 0 11h digital filter select 1 0 0 lpf hpf 0 0 0 hpfad 12h reserved 0 0 0 0 0 0 0 0 13h reserved 0 0 0 0 0 0 0 0 14h reserved 0 0 0 0 0 0 0 0 15h reserved 0 0 0 0 0 0 0 0 16h reserved 0 0 0 0 0 0 0 0 17h reserved 0 0 0 0 0 0 0 0 18h reserved 0 0 0 0 0 0 0 0 19h reserved 0 0 0 0 0 0 0 0 1ah reserved 0 0 0 0 0 0 0 0 1bh reserved 0 0 0 0 0 0 0 0 1ch hpf co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 1dh hpf co-efficient 1 0 0 f1a13 f1a12 f1a11 f1a10 f1a9 f1a8 1eh hpf co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 1fh hpf co-efficient 3 0 0 f1b13 f1b12 f1b11 f1b10 f1b9 f1b8 20h beep frequency bpcnt 0 0 0 0 0 bpfr1 bpfr0 21h beep on time bpon7 bpon6 bpon5 bpon4 bpon3 bpon2 bpon1 bpon0 22h beep off time bpoff7 bpoff6 bpoff5 bpoff4 bpoff3 bpoff2 bpoff1 bpoff0 23h beep repeat count 0 bptm6 b ptm5 bptm4 bptm3 bptm2 bptm1 bptm0 24h beep vol/control bpout 0 0 0 0 bplvl2 bplvl1 bplvl0 25h reserved 0 0 0 0 0 0 0 0 26h reserved 0 0 0 0 0 0 0 0 27h reserved 0 0 0 0 0 0 0 0 28h reserved 0 0 0 0 0 0 0 0 29h reserved 0 0 0 0 0 0 0 0 2ah reserved 0 0 0 0 0 0 0 0 2bh reserved 0 0 0 0 0 0 0 0 2ch lpf co-efficient 0 f2a7 f2a6 f2a5 f2a4 f2a3 f2a2 f2a1 f2a0 2dh lpf co-efficient 1 0 0 f2a13 f2a12 f2a11 f2a10 f2a9 f2a8 2eh lpf co-efficient 2 f2b7 f2b6 f2b5 f2b4 f2b3 f2b2 f2b1 f2b0 2fh lpf co-efficient 3 0 0 f2b13 f2b12 f2b11 f2b10 f2b9 f2b8
[ak4634] rev. 0.5 2007/10 - 61 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 30h digital filter select 2 0 0 0 eq5 eq4 eq3 eq2 eq1 31h reserved 0 0 0 0 0 0 0 0 32h e1 co-efficient 0 e1a7 e1a6 e1a5 e1a4 e1a3 e1a2 e1a1 e1a0 33h e1 co-efficient 1 e1a15 e1a14 e1 a13 e1a12 e1a11 e1a10 e1a9 e1a8 34h e1 co-efficient 2 e1b7 e1b6 e1b5 e1b4 e1b3 e1b2 e1b1 e1b0 35h e1 co-efficient 3 e1b15 e1b14 e1b13 e1b12 e1b11 e1b10 e1b9 e1b8 36h e1 co-efficient 4 e1c7 e1c6 e1c5 e1c4 e1c3 e1c2 e1c1 e1c0 37h e1 co-efficient 5 e1c15 e1c14 e1c13 e1c12 e1c11 e1c10 e1c9 e1c8 38h e2 co-efficient 0 e2a7 e2a6 e2a5 e2a4 e2a3 e2a2 e2a1 e2a0 39h e2 co-efficient 1 e2a15 e2a14 e2 a13 e2a12 e2a11 e2a10 e2a9 e2a8 3ah e2 co-efficient 2 e2b7 e2b6 e2b5 e2b4 e2b3 e2b2 e2b1 e2b0 3bh e2 co-efficient 3 e2b15 e2b14 e2b13 e2b12 e2b11 e2b10 e2b9 e2b8 3ch e2 co-efficient 4 e2c7 e2c6 e2c5 e2c4 e2c3 e2c2 e2c1 e2c0 3dh e2 co-efficient 5 e2c15 e2c14 e2c13 e2c12 e2c11 e2c10 e2c9 e2c8 3eh e3 co-efficient 0 e3a7 e3a6 e3a5 e3a4 e3a3 e3a2 e3a1 e3a0 3fh e3 co-efficient 1 e3a15 e3a14 e3 a13 e3a12 e3a11 e3a10 e3a9 e3a8 40h e3 co-efficient 2 e3b7 e3b6 e3b5 e3b4 e3b3 e3b2 e3b1 e3b0 41h e3 co-efficient 3 e3b15 e3b14 e3b13 e3b12 e3b11 e3b10 e3b9 e3b8 42h e3 co-efficient 4 e3c7 e3c6 e3c5 e3c4 e3c3 e3c2 e3c1 e3c0 43h e3 co-efficient 5 e3c15 e3c14 e3c13 e3c12 e3c11 e3c10 e3c9 e3c8 44h e4 co-efficient 0 e4a7 e4a6 e4a5 e4a4 e4a3 e4a2 e4a1 e4a0 45h e4 co-efficient 1 e4a15 e4a14 e4 a13 e4a12 e4a11 e4a10 e4a9 e4a8 46h e4 co-efficient 2 e4b7 e4b6 e4b5 e4b4 e4b3 e4b2 e4b1 e4b0 47h e4 co-efficient 3 e4b15 e4b14 e4b13 e4b12 e4b11 e4b10 e4b9 e4b8 48h e4 co-efficient 4 e4c7 e4c6 e4c5 e4c4 e4c3 e4c2 e4c1 e4c0 49h e4 co-efficient 5 e4c15 e4c14 e4c13 e4c12 e4c11 e4c10 e4c9 e4c8 4ah e5 co-efficient 0 e5a7 e5a6 e5a5 e5a4 e5a3 e5a2 e5a1 e5a0 4bh e5 co-efficient 1 e5a15 e5a14 e5a13 e5a12 e5a11 e5a10 e5a9 e5a8 4ch e5 co-efficient 2 e5b7 e5b6 e5b5 e5b4 e5b3 e5b2 e5b1 e5b0 4dh e5 co-efficient 3 e5b15 e5b14 e5b13 e5b12 e5b11 e5b10 e5b9 e5b8 4eh e5 co-efficient 4 e5c7 e5c6 e5c5 e5c4 e5c3 e5c2 e5c1 e5c0 4fh e5 co-efficient 5 e5c15 e5c14 e5c13 e5c12 e5c11 e5c10 e5c9 e5c8 the pdn pin = ?l? resets the registers to their default values. note 39. ?0? bits must contain ?0? and the ?1? bits must contain ?1? value. note 40. reading of address 12h ~ 1fh, 25h ~ 2fh and 31h ~ 4fh are not possible. note 41. 0fh and 0dh are for address read only. however, 0dh address cannot be read at i 2 c ?bus control mode. writing access to 0dh and 0fh doe s not effect the operation.
[ak4634] rev. 0.5 2007/10 - 62 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 pmpfil pmvcm 0 pmspk pmao pmdac 0 pmadc r/w r/w r/w r r/ w r/w r/w r r/w default 0 0 0 0 0 0 0 0 pmadc: adc block power control 0: power down (default) 1: power up when the pmadc bit changes from ?0 ? to ?1?, the initialization cycle (1059/fs=133ms@8khz) starts. after initializing, digital data of the adc is output. pmdac: dac block power control 0: power down (default) 1: power up pmao: mono line out power control 0: power down (default) 1: power up pmspk: speaker block power control 0: power down (default) 1: power up pmvcm: vcom block power control 0: power down (default) 1: power up pmpfil: programmable filter block (hpf/ lpf/ 5-band eq/ alc) power control 0: power down (default) 1: power up each block can be powered-down respectiv ely by writing ?0? to each bit. when the pdn pin is ?l?, all blocks are powered-down. when pmpll and mcko bits and all bits in 00h address are ?0?, all blocks are powered-down. when any of the blocks are powered- up, the pmvcm bit must be set to ?1?. when pmpll and mcko bits and all bits in 00h address are ?0 ?, pmvcm bit can be ?0?. when any block of adc, dac, spk, or programmable digital filter is powered-up (pmadc bit = ?1?or pmdac bit = ?1? or pmspk bit = ?1? pm pfil bit = ?1?), the clocks must always be present.
[ak4634] rev. 0.5 2007/10 - 63 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h power management 2 0 0 0 0 m/s 0 mcko pmpll r/w r/w r r r r/w r r/w r/w default 0 0 0 0 0 0 0 0 pmpll: pll block po wer control select 0: pll is power down and exte rnal is selected. (default) 1: pll is power up and pll mode is selected. mcko: master clock output enable 0: ?l? output (default) 1: 256fs output m/s: select master/ slave mode 0: slave mode (default) 1: master mode addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h signal select 1 spoute 0 dac s daca mgain3 pmmp mgain2 mgain0 r/w r/w r r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 1 mgain3-2: mic-amp gain control ( table 20 ) mgain1 bit is located at d5 bit of 03h. default: ?0001? (+20.0db) pmmp: mpi pin power control 0: power down (default) 1: power up when pmadc bit is ?1?, pmmp bit is enabled. daca: switch control from dac to mono line amp 0: off (default) 1: on when pmao bit is ?1?, daca bit is enabled. when pmao bit is ?0?, the aout pin goes vss1. dacs: switch control from dac to speaker-amp 0: off (default) 1: on when dacs bit is ?1?, dac output signal is input to speaker-amp. spoute: speaker output signal enable 0: disable (default) 1: enable when spoute bit is ?0?, the spp and spn pins output vss3. when spoute bit is ?1?, the spp and spn pins output signal.
[ak4634] rev. 0.5 2007/10 - 64 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h signal select 2 pfsdo aops mgain1 0 spkg 0 pfdac adcpf r/w r/w r/w r/w r r/w r r/w r/w default 1 0 0 0 0 0 0 1 adcpf: select of input signal to programmable filter/alc. 0: sdti 1: output of adc (default) pfdac: select of input signal to dac. 0: sdti (default) 1: output of programmable filter/alc spkg: select speaker-amp output gain 0: 0db (default) 1: +2db mgain1: mic-amplifier gain control ( table 20 ) mgain3-2 and mgain0 bits are d3, d2 and d0 of 02h. default: ?0001? (+20.0db) aops: mono line output power-save mode 0: normal operation (default) 1: power-save mode power-save mode is enable at aops bit = ?1?. pop noi se at power-up/down can be reduced by changing at pmao bit = ?1?. ( figure 42 ) pfsdo: select of signal from sdto 0: output of adc (1 st - hpf) 1: output of programmable filter/alc (default) addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h mode control 1 pll3 pll2 pll1 pll0 bcko1 bcko0 dif1 dif0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 dif1-0: audio interface format ( table 16 ) default: ?10? (msb first) bcko1-0: select bick output frequency at master mode ( table 9 ) default: ?00? (16fs) pll3-0: select input frequency at pll mode ( table 4 ) default: ?0000? (fck pin)
[ak4634] rev. 0.5 2007/10 - 65 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h mode control 2 adrst fcko fs3 msbs bckp fs2 fs1 fs0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 fs3-0: setting of sampling frequency ( table 5 and table 6 ) and mcki frequency ( table 11 ) these bits are selected to sampling frequency at pll mode and mcki frequency at ext mode. default: ?0000? bckp, msbs: ?00? (default) ( table 17 ) fcko: select fck output frequency at master mode ( table 10 ) default: ?0? adrst: initialization cycle setting of adc 0: 1059/fs (default) 1: 291/fs addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h timer select 0 wtm2 ztm 1 ztm0 wtm1 wtm0 rfst1 rfst0 r/w r r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 wtm2-0: alc1 recovery waiting period ( table 28 ) a period of recovery operation when any limiter ope ration does not occur during the alc1 operation. default is ?000?. ztm1-0: alc1, alc2, ivol and ovol zero crossing timeout period ( table 27 ) the gain is changed by the manual volume controlling (a lc off) or the recovery operation (alc on) only at zero crossing or timeout. the default value is ?00?. rfst1-0 : alc first recovery speed ( table 32 ) default: ?00? (4times)
[ak4634] rev. 0.5 2007/10 - 66 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h alc mode control 1 lfst alc2 alc1 zelmn lmat1 lmat0 rgain0 lmth0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 1 lmth1-0: alc limiter detection level / recovery waiting counter reset level ( table 25 ) lmth1 bit is located at d6 bit of 0bh. default: ?01? rgain1-0: alc recovery gain step ( table 29 ) rgain1 bit is located at d7 bit of 0bh. default: ?00? lmat1-0: alc limiter att step ( table 26 ) default: ?00? zelmn: zero crossing detection en able at alc limiter operation 0: enable (default) 1: disable alc1: alc of recoding path enable 0: disable (default) 1: enable alc2: alc2 of playback path enable 0: disable (default) 1: enable lfst: limiter function of alc when the output was bigger than fs. 0: the volume value is changed at zero crossing or timeout. (default) 1: when output of alc is bigger than fs, vol value is changed instantly. addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h alc mode control 2 iref7 iref6 iref5 iref4 iref3 iref2 iref1 iref0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 1 0 0 0 1 0 1 iref7-0: reference value at alc recovery ope ration for recoding. (0.375db step, 242 level) ( table 30 ) default: ?c5h? (+19.5db)
[ak4634] rev. 0.5 2007/10 - 67 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h input digital volume control ivol 7 ivol6 ivol5 ivol4 ivol 3 ivol2 ivol1 ivol0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 0 0 1 0 0 0 1 ivol7-0: input digital volume; 0.375db step, 242 level ( table 22 ) default: ?91h? (0.0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah digital volume control ovol 7 ovol6 ovol5 ovol4 ovol 3 ovol2 ovol1 ovol0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 0 0 1 0 0 0 1 ovol7-0: output digital volume; 0.375db step, 242 level ( table 23 ) default: ?91h? (0.0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh alc mode control 3 rgain1 lmth1 oref5 oref4 oref3 oref2 oref1 oref0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 1 0 1 0 0 0 oref5-0: reference value at alc recovery operation for playback. 1.5db step, 60 level ( table 31 ) default: ?28h? (+6.0db) lmth1-0: alc limiter detection level / recovery waiting counter reset level ( table 25 ) default: ?01? (-4.1dbfs > alc output -6.0dbfs) rgain1-0: alc recovery gain step ( table 29 ) rgain1 bit is located at d1 bit of 07h. default: ?00? addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh input digital volume control vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 r/w r r r r r r r r default - - - - - - - - vol7-0: the current volume of alc; 0.375db step, 242 level, read only ( table 33 )
[ak4634] rev. 0.5 2007/10 - 68 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh mode control 3 datt1 datt0 smute mdif 1 0 1 read r/w r/w r/w r/w r/w r r r r/w default 0 0 0 0 1 0 1 0 read: read function enable 0: disable (default) 1: enable mdif: single-ended / full-differential input select 0: single-ended input (mic pin or lin pin: default) 1: full-differential input (micp and micn pins) smute: soft mute control 0: normal operation (default) 1: dac outputs soft-muted datt1-0: output digital volume2; 6db step, 4 level ( table 24 ) default: ?00h? (0.0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0fh thermal shutdown thdet 0 0 0 0 0 0 0 r/w r r r r r r r r default 0 0 0 0 0 0 0 0 thdet: thermal shutdown detection 0: normal operation (default) 1: thermal shutdown addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h signal select 4 0 lovl 0 0 0 0 lin 0 r/w r r/w r r r r r/w r default 0 0 0 0 0 0 0 0 lin: select input data of adc 0: mic pin (default) 1: lin pin lovl: lineout gain setting 0: 0db(default) 1: +2db
[ak4634] rev. 0.5 2007/10 - 69 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 11h digital filter select 1 0 0 lpf hpf 0 0 0 hpfad r/w r r r/w r/w r r r r/w default 0 0 0 1 0 0 0 1 hpfad: hpf enable in adc block 0: disable when hpfad bit is ?0?, hpfad block is bypassed (0db). 1: enable (default) when hpfad bit is ?1?, f1a 13-0, f1b13-0 bits are enabled. hpfad bit should be ?1?at pmadc bit = ?1?. hpf: hpf enable in filter block. 0: disable when hpf bit is ?0?, hpf block is bypassed (0db). 1: enable (default) when hpf bit is ?1?, f1a13- 0, f1b13-0 bits are enabled. lpf: lpf coefficient setting enable 0: disable (default) when lpf bit is ?0?, lpf block is bypassed (0db). 1: enable when lpf bit is ?1?, f2a13-0, f2b13-0 bits are enabled. addr register name d7 d6 d5 d4 d3 d2 d1 d0 1ch hpf co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 1dh hpf co-efficient 1 0 0 f1a13 f1a12 f1a11 f1a10 f1a9 f1a8 1eh hpf co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 1fh hpf co-efficient 3 0 0 f1b13 f1b12 f1b11 f1b10 f1b9 f1b8 r/w w w w w w w w w default f1a13-0 bits = 0x1f16, f1b13-0 bits = 0x1e2b f1a13-0, f1b13-0: fil1 (wind-noise reduction filter) coefficient (14bit x 2) default: f1a13-0 bits = 0x1f16, f1b13-0 bits = 0x1e2b fc = 75hz@fs = 8khz, 150hz@fs = 16khz addr register name d7 d6 d5 d4 d3 d2 d1 d0 20h beep frequency bpcnt 0 0 0 0 0 bpfr1 bpfr0 r/w r/w r r r r r r/w r/w default 0 0 0 0 0 0 0 0 bpfr1-0: beep signal output frequency setting ( table 38 ~ table 40 ) default: ?00? bpcnt: beep signal output mode setting 0: once output mode (default) 1: continuous mode in continuous mode, the beep signal is output while bpcnt bit is ?1?. in output mode, the beep signal is output by only the frequency set with bptm6-0 bits.
[ak4634] rev. 0.5 2007/10 - 70 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 21h beep on time bpon7 bpon6 bpon5 bpon4 bpon3 bpon2 bpon1 bpon0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bpon7-0: setting on-time of beep signal output ( table 41 ) default: ?00h? addr register name d7 d6 d5 d4 d3 d2 d1 d0 22h beep off time bpoff7 bpoff6 bpoff5 bpoff4 bpoff3 bpoff2 bpoff1 bpoff0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bpoff7-0: setting off-time of beep signal output ( table 42 ) default: ?00h? addr register name d7 d6 d5 d4 d3 d2 d1 d0 23h beep repeat count 0 bptm6 b ptm5 bptm4 bptm3 bptm2 bptm1 bptm0 r/w r r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bptm6-0: setting the number of times that beep signal repeats ( table 43 ) default: ?00h? addr register name d7 d6 d5 d4 d3 d2 d1 d0 24h beep vol/control bpout 0 0 0 0 bplvl2 bplvl1 bplvl0 r/w r/w r r r r r/w r/w r/w default 0 0 0 0 0 0 0 0 bplvl2-0: setting output level of beep signal ( table 44 ) default: ?0h? (0db) bpout: beep signal control 0: off (default) 1: on at the time of bpcnt = ?0?, when bp out bit is ?1?, the beep signal starts outputting. the beep signal stops after the number of times that was set in bptm6-0 bit, and bpout bit is set to ?0? automatically.
[ak4634] rev. 0.5 2007/10 - 71 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 2ch lpf co-efficient 0 f2a7 f2a6 f2a5 f2a4 f2a3 f2a2 f2a1 f2a0 2dh lpf co-efficient 1 0 0 f2a13 f2a12 f2a11 f2a10 f2a9 f2a8 2eh lpf co-efficient 2 f2b7 f2b6 f2b5 f2b4 f2b3 f2b2 f2b1 f2b0 2fh lpf co-efficient 3 0 0 f2b13 f2b12 f2b11 f2b10 f2b9 f2b8 r/w w w w w w w w w default 0 0 0 0 0 0 0 0 f2a13-0, f2b13-0: lpf coefficient (14bit x 2) default: ?0000h? addr register name d7 d6 d5 d4 d3 d2 d1 d0 30h digital filter select 2 0 0 0 eq5 eq4 eq3 eq2 eq1 r/w r r r r/w r/ w r/w r/w r/w default 0 0 0 0 0 0 0 0 eq1: equalizer 1 coefficient setting enable 0: disable (default) when eq1 bit is ?0?, eq block is through (0db). 1: enable when eq1 bit is ?1?, e1a15-0, e1b15-0, e1c15-0 bits are enabled. eq2: equalizer 2 coefficient setting enable 0: disable (default) when eq2 bit is ?0?, eq block is through (0db). 1: enable when eq2 bit is ?1?, e2a15-0, e2b15-0, e2c15-0 bits are enabled. eq3: equalizer 3 coefficient setting enable 0: disable (default) when eq3bit is ?0?, eq block is through (0db). 1: enable when eq3 bit is ?1?, e3a15-0, e3b15-0, e3c15-0 bits are enabled. eq4: equalizer 4 coefficient setting enable 0: disable (default) when eq4 bit is ?0?, eq block is through (0db). 1: enable when eq4 bit is ?1?, e4a15-0, e4b15-0, e4c15-0 bits are enabled. eq5: equalizer 5 coefficient setting enable 0: disable (default) when eq5 bit is ?0?, eq block is through (0db). 1: enable when eq5 bit is ?1?, e5a15-0, e5b15-0, e5c15-0 bits are enabled.
[ak4634] rev. 0.5 2007/10 - 72 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 32h e1 co-efficient 0 e1a7 e1a6 e1a5 e1a4 e1a3 e1a2 e1a1 e1a0 33h e1 co-efficient 1 e1a15 e1a14 e1a13 e1a12 e1a11 e1a10 e1a9 e1a8 34h e1 co-efficient 2 e1b7 e1b6 e1b5 e1b4 e1b3 e1b2 e1b1 e1b0 35h e1 co-efficient 3 e1b15 e1b14 e1b13 e1b12 e1b11 e1b10 e1b9 e1b8 36h e1 co-efficient 4 e1c7 e1c6 e1c5 e1c4 e1c3 e1c2 e1c1 e1c0 37h e1 co-efficient 5 e1c15 e1c14 e1c13 e1c12 e1c11 e1c10 e1c9 e1c8 38h e2 co-efficient 0 e2a7 e2a6 e2a5 e2a4 e2a3 e2a2 e2a1 e2a0 39h e2 co-efficient 1 e2a15 e2a14 e2a13 e2a12 e2a11 e2a10 e2a9 e2a8 3ah e2 co-efficient 2 e2b7 e2b6 e2b5 e2b4 e2b3 e2b2 e2b1 e2b0 3bh e2 co-efficient 3 e2b15 e2b14 e2b13 e2b12 e2b11 e2b10 e2b9 e2b8 3ch e2 co-efficient 4 e2c7 e2c6 e2c5 e2c4 e2c3 e2c2 e2c1 e2c0 3dh e2 co-efficient 5 e2c15 e2c14 e2c13 e2c12 e2c11 e2c10 e2c9 e2c8 3eh e3 co-efficient 0 e3a7 e3a6 e3a5 e3a4 e3a3 e3a2 e3a1 e3a0 3fh e3 co-efficient 1 e3a15 e3a14 e3a13 e3a12 e3a11 e3a10 e3a9 e3a8 40h e3 co-efficient 2 e3b7 e3b6 e3b5 e3b4 e3b3 e3b2 e3b1 e3b0 41h e3 co-efficient 3 e3b15 e3b14 e3b13 e3b12 e3b11 e3b10 e3b9 e3b8 42h e3 co-efficient 4 e3c7 e3c6 e3c5 e3c4 e3c3 e3c2 e3c1 e3c0 43h e3 co-efficient 5 e3c15 e3c14 e3c13 e3c12 e3c11 e3c10 e3c9 e3c8 44h e4 co-efficient 0 e4a7 e4a6 e4a5 e4a4 e4a3 e4a2 e4a1 e4a0 45h e4 co-efficient 1 e4a15 e4a14 e4a13 e4a12 e4a11 e4a10 e4a9 e4a8 46h e4 co-efficient 2 e4b7 e4b6 e4b5 e4b4 e4b3 e4b2 e4b1 e4b0 47h e4 co-efficient 3 e4b15 e4b14 e4b13 e4b12 e4b11 e4b10 e4b9 e4b8 48h e4 co-efficient 4 e4c7 e4c6 e4c5 e4c4 e4c3 e4c2 e4c1 e4c0 49h e4 co-efficient 5 e4c15 e4c14 e4c13 e4c12 e4c11 e4c10 e4c9 e4c8 4ah e5 co-efficient 0 e5a7 e5a6 e5a5 e5a4 e5a3 e5a2 e5a1 e5a0 4bh e5 co-efficient 1 e5a15 e5a14 e5a13 e5a12 e5a11 e5a10 e5a9 e5a8 4ch e5 co-efficient 2 e5b7 e5b6 e5b5 e5b4 e5b3 e5b2 e5b1 e5b0 4dh e5 co-efficient 3 e5b15 e5b14 e5b13 e5b12 e5b11 e5b10 e5b9 e5b8 4eh e5 co-efficient 4 e5c7 e5c6 e5c5 e5c4 e5c3 e5c2 e5c1 e5c0 4fh e5 co-efficient 5 e5c15 e5c14 e5c13 e5c12 e5c11 e5c10 e5c9 e5c8 r/w w w w w w w w w default 0 0 0 0 0 0 0 0 e1a15-0, e1b15-0, e1c15-0: equalizer 1 coefficient (16bit x3) default: ?0000h? e2a15-0, e2b15-0, e2c15-0: equalizer 2 coefficient (16bit x3) default: ?0000h? e3a15-0, e3b15-0, e3c15-0: equalizer 3 coefficient (16bit x3) default: ?0000h? e4a15-0, e4b15-0, e4c15-0: equalizer 4 coefficient (16bit x3) default: ?0000h? e5a15-0, e5b15-0, e5c15-0: equalizer 5 coefficient (16bit x3) default: ?0000h?
[ak4634] rev. 0.5 2007/10 - 73 - system design figure 57 and figure 58 show the system connection diagram. the evaluation board [AKD4634] demonstrates the optimum layout, power supply arrangements and measurement results. < mic single-end input > top vie w avdd nc mcko analog supply 2.2 3.6v 0.1 2.2k speaker cp 0.1 dsp & p zd1 vss1 tst1 tst3 pdn csn tst2 vcom vcoc fck cclk cdti mpi mic lin aout mcki sdti bick vss3 vss2 dvdd i2c spp svdd spn sdto rp + 10 0.1 + 2.2 1 1 220 20 k r2 r1 zd2 0.1 dynamic spk r1, r2: short zd1, zd2: open piezo spk r1, r2: 10 zd1, zd2: required 10 1 figure 57. typical connection diagram notes: - vss1, vss2 and vss3 of the ak4634 should be distributed separately from the ground of external controllers. - all digital input pins except pull-down pin should not be left floating. - in ext mode (pmpll bit = ?0?), rp and cp of the vcoc pin can be open. - in pll mode (pmpll bit = ?1?), rp and cp of the vcoc pin should be connected as shown in table 45 . - when the ak4634 is used at master mode, fck and bick pins are floating before m/s bit is changed to ?1?. therefore, a pull-up resistor with around 100 ? should be connected to lrck and bick pins of the ak4634. -when avdd, dvdd and svdd were distributed, dvdd = 1.6 ~ 3.6 v, svdd = 2.2 ~ 4.0 v.
[ak4634] rev. 0.5 2007/10 - 74 - < mic differential input > top vie w avdd nc mcko analog supply 2.2 3.6v 0.1 1k speaker cp 0.1 dsp & p zd1 vss1 tst1 tst3 pdn csn tst2 vcom vcoc fck cclk cdti mpi micp micn aout mcki sdti bick vss3 vss2 dvdd i2c spp svdd spn sdto rp + 10 0.1 + 2.2 1 1 220 20 k r2 r1 zd2 0.1 dynamic spk r1, r2: short zd1, zd2: open piezo spk r1, r2: 10 zd1, zd2: required 10 1k 1 figure 58. typical connection diagram notes: - vss1, vss2 and vss3 of the ak4634 should be distributed separately from the ground of external controllers. - all digital input pins except pull-down pin should not be left floating. - in ext mode (pmpll bit = ?0?), rp and cp of the vcoc pin can be open. - in pll mode (pmpll bit = ?1?), rp and cp of the vcoc pin should be connected as shown in table 45 . - when the ak4634 is used at master mode, fck and bick pins are floating before m/s bit is changed to ?1?. therefore, a pull-up resistor with around 100 ? should be connected to lrck and bick pins of the ak4634. -when avdd, dvdd and svdd were distributed, dvdd = 1.6 ~ 3.6 v, svdd = 2.2 ~ 4.0 v. rp and cp of vcoc pin pll lock time (max) mode pll3 bit pll2 bit pll1 bit pll0 bit pll reference clock input pin input frequency rp[ ] cp[f] 0 0 0 0 0 fck pin 1fs 6.8k 220n 160ms (default) 1 0 0 0 1 bick pin 16fs 10k 4.7n 2ms 2 0 0 1 0 bick pin 32fs 10k 4.7n 2ms 3 0 0 1 1 bick pin 64fs 10k 4.7n 2ms 6 0 1 1 0 mcki pin 12mhz 10k 4.7n 30ms 7 0 1 1 1 mcki pin 24mhz 10k 4.7n 30ms 12 1 1 0 0 mcki pin 13.5mhz 10k 10n 30ms 13 1 1 0 1 mcki pin 27mhz 10k 10n 30ms others others n/a table 45. setting of pll mode (*fs: sampling frequency, n/a: not available)
[ak4634] rev. 0.5 2007/10 - 75 - 1. grounding and power supply decoupling the ak4634 requires careful attention to power s upply and grounding arrangements. avdd, dvdd and svdd are usually supplied from the system?s analog supply. if avdd, dvdd and svdd are supplied separately, the correct power up sequence should be observevss21, vss2 and vss3 of the ak4634 should be connected to the analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak4634 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference vcom is a signal ground of this chip. a 2.2 f electrolytic capacitor in parallel with a 0.1 f ceramic capacitor attached to the vcom pin eliminates the effects of high frequency noise. no load current may be drawn from the vcom pin. all signals, especially clocks, should be kept away from the vcom pin in order to avoid unwanted coupling into the ak4634. 3. analog inputs the mic and line inputs supports single-ended and differential. the input signal range scales with nominally at 0.06 x avdd vpp for the mic input and 0.6 x avdd vpp for the beep input, centered around the internal common voltage (approx. 0.45 x avdd). usually the input signal is ac coupled using a capacitor. the cut-off frequency is fc = (1/2 rc). the ak4634 can accept input voltages from vss1 to avdd. 4. analog outputs the input data format for the dac is 2?s complement. th e output voltage is a positive full scale for 7fffh(@16bit) and a negative full scale for 8000h(@16bit). mono line output from the aout pin is centered at 0.45 x avdd (typ).
[ak4634] rev. 0.5 2007/10 - 76 - package 29pin wl-csp : 2.5mm x 3.0mm 0.5 0.3 0.05 0.08 s s 0.05 ab s b m a 0.85 0.25 e dc b a 3.0 0.1 1 2 4 5 3 6 a b c d e top view bottom view 4634 xxxx 2.5 0.1 1 2 4 5 3 6
[ak4634] rev. 0.5 2007/10 - 77 - marking 4634 xxxx a 1 xxxx: date code (4 digits) important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akemd products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akemd pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above cont ent and conditions, and the buyer or distributor agrees to assume any and all re sponsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification.

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